[darkmatter]

Hi,


Any technical comments or opinions about that?

Regards
Darkmatter

[D'Espice]

1 GHz effective bandwith means it's a 1 GHz DDR bus which means it's really only a 500 MHz bus - but doesn't matter since it's DDR.

[Footy]

One more time for us stupid people but this time slowly. Are you saying Apple is trying to out smart us.

-Footy

Originally posted by D'Espice:
1 GHz effective bandwith means it's a 1 GHz DDR bus which means it's really only a 500 MHz bus - but doesn't matter since it's DDR.

[Mac Zealot]

Give em credit, D` up until a few months ago intel/amd's fastest bus was 533mhz and THAT was ddr.

The current crop is 800mhz (400mhzx2 or is it 200mhzx4 I have no idea).

But that's still no match for the *gasp* PowerMac 970, a marvel of graphics and sound!

*turns it on*
DOOT DOOT DOOT DOO!!!!
*sees crappy 2bit screen*

[galarneau]

THe fastest DDR RAM I'm aware of is PC3700, which runs at 466MHz, which (as it is DDR), translates into a 933MHz bus.

So.... if Apple is selling a 1GHz FSB machine, I'm not sure where we're gonna get RAM for it (aside from Apple's inflated prices).

Is anyone aware of RAM that runs at a faster speed?

[quadgrande]

The PPC970 has a FSB that is 1/2 of the processor speed. Therefor the 1.6 Ghz will have an 800 Mhz FSB, the 1.8 900, and the 2.0 GHz a 1GHz FSB. There's a memory controller between the bus and the actual RAM which handles buffering, etc (ala North Bridge), so the bus doesn't connect directly to the memory.

[D'Espice]

Originally posted by galarneau:
THe fastest DDR RAM I'm aware of is PC3700, which runs at 466MHz, which (as it is DDR), translates into a 933MHz bus.

So.... if Apple is selling a 1GHz FSB machine, I'm not sure where we're gonna get RAM for it (aside from Apple's inflated prices).

Is anyone aware of RAM that runs at a faster speed?

Wrong wrong wrong. PC3700 is 466 MHz DDR = 2 x 233 MHz SDR

SDR = Single Data Rate
DDR = Double Data Rate

Intel Pentium 4: 800 MHz FSB quad-pumped aka 4 x 200 MHz SDR
AMD Athlon XP: 400 MHz DDR aka 2 x 200 MHz SDR
IBM PowerPC 970: 1/2 CPU-speed DDR aka 2 x 1/4 CPU-speed SDR

Which means that a 2 GHz CPU has an effective frontside bus of 1 GHz yet since it's DDR we're not talking about 1000 real MHz but 2 x 500 MHz SDR = 1 GHz DDR.

And that RAM thing above is wrong, wrong wrong. Current DDR-RAM is PC2700 / DDR333 which means that it's 333 MHz DDR aka 2 x 166 MHz SDR. Same with PC3700 / DDR466 which means that it's 466 MHz DDR aka 2 x 233 MHz SDR.

DDR SDRAM (DDR200, DDR266, ...) reads on both the rising and the falling edges of the clock signal whereas standard SDR SDRAM (PC66, PC100, PC133) only reads the falling edge. In other words this means that DDR SDRAM is twice as fast as SDR SDRAM even though clock speed has not to be increased, hence the confusion.
Apparantly some marketing division of some company whose name I mysteriously forgot thought it was cool to tell people that they have REAL 266 MHz instead of telling them the truth about 133 MHz DDR

[galarneau]

Originally posted by D'Espice:
Wrong wrong wrong. PC3700 is 466 MHz DDR = 2 x 233 MHz SDR

ok man, chill.... apologies for being wrong. Hey, it happens sometimes... maybe even to you one day. Maybe.

[forcelite]

wouldnt you still need 250 MHZ ram being 1/4 of 1ghz =250mhz

And that being said the fastest ram availne is 233mhz whcih is extremely overclocked and more volitile with each mhz increase.

Dont get me wrong I belive apple can do it but I think some info is missing

Force

[Scotttheking]

Current fast PCs use PC3200, which runs at 200MHz (400MHz effective)
On intel's new motherboards, it's dual channel, which gives 400MHz (800MHz effective).
On their FSB, it's 200MHzx4 for most instructions, so that's 800MHz effective.

There really isn't anything faster then PC3200 that's remotely a standard (has PC3200 even been approved?).
Now, something interesting. They say 8GB of ram.
Crucial only has up to 512MB PC3200 and PC2700 sticks, but their PC2100 goes up to 2GB.

Now, with the 970 bus scaling with the processor, that means that you divide the clock speed by two to get the effective MHz of the bus. Since the bus is double pumped, you divide by two again to get the actual MHz.

About ram speed. The bus is faster then current ram, yes. However, apple could put L3 cache on the northbridge (memory controller), which could be 16MB or so, and that would provide a faster interface. Or they could just make it so that the memory bandwidth (assumed 800MHz effective) is the limiting factor.

Any questions, just ask.

[Eug]

I'm still thinking that what it means is that the machine is capable of "up to 1 GHz" FSB (ie. 250x2 dual channel), but that it will ship with DDR400 (ie. 800 MHz).

Perhaps with some sort of jumper setting or whatever one can change it to 1 GHz (at least with the 2 GHz dual PPC 970) when the memory becomes available.

Last edited by Eug talking out of his ass on 06-23-2003 at 11:31 PM.

[Scotttheking]

Originally posted by Eug:
I'm still thinking that what it means is that the machine is capable of "up to 1 GHz" FSB (ie. 250x2 dual channel), but that it will ship with DDR400 (ie. 800 MHz).

Perhaps with some sort of jumper setting or whatever one can change it to 1 GHz (at least with the 2 GHz dual PPC 970) when the memory becomes available.

Last edited by Eug talking out of his ass on 06-23-2003 at 11:31 PM.

Or it could be like the nforce2 mobos, which will detect what ram you have and run at that speed.
I'm personally hoping for 8-16MB of L3 cache on the northbridge.

[jcadam]

hehe, it says

"up to 1GHz processor bus"

I remember back in the day when I built myself a 600mhz Athlon (older, big cartridge package CPU) system. I got a new motherboard with the VIA KX133 chipset. This swell chipset could run the processor FSB and memory bus asynchronously (the first Athlon chipset to have this capability).

This made it possible to run the Athlon, which, at the time had a 100MHz (200 MHz DDR) bus with PC133 (133MHz SDR) memory, without slowing the RAM down to 100Mhz.

the FSB and memory bus don't HAVE to run at the same clock rate.

[Scotttheking]

Originally posted by jcadam:
hehe, it says

"up to 1GHz processor bus"

I remember back in the day when I built myself a 600mhz Athlon (older, big cartridge package CPU) system. I got a new motherboard with the VIA KX133 chipset. This swell chipset could run the processor FSB and memory bus asynchronously (the first Athlon chipset to have this capability).

This made it possible to run the Athlon, which, at the time had a 100MHz (200 MHz DDR) bus with PC133 (133MHz SDR) memory, without slowing the RAM down to 100Mhz.

the FSB and memory bus don't HAVE to run at the same clock rate.

The 970 FSB multiplier is 4X. As the processor scales, the FSB does too.
That's why it's "up to 1ghz"

[Eug]

Originally posted by Scotttheking:
Or it could be like the nforce2 mobos, which will detect what ram you have and run at that speed.
I'm personally hoping for 8-16MB of L3 cache on the northbridge.

Your nForce2 comment makes sense, but aren't the PPC 970 designs supposed to have no L3?

[Scotttheking]

Originally posted by Eug:
Your nForce2 comment makes sense, but aren't the PPC 970 designs supposed to have no L3?

There is no L3 interface on the chip. That doesn't stop anyone from putting L3 on the northbridge.

If we assume IBM is making the chip, it wouldn't have all of apple's I/O ports on it. Apple could be linking the northbridge and the southbridge via HT, and the northbridge would then have room for the L3 cache (the pins it has require it to be at least a certain size)

[power142]

I wouldn't rule out L3 on the north bridge, but an L2 cache of sufficient size and that high-speed bus could make it irrelevant.

[kupan787]

Originally posted by Eug:
I'm still thinking that what it means is that the machine is capable of "up to 1 GHz" FSB (ie. 250x2 dual channel), but that it will ship with DDR400 (ie. 800 MHz).

I am not sure what you are saying by 250x2 dual channel (do you mean you think it is 250MHz quad pumped?)

As far aas I underdstand that 970 bus runs at 1/4 the processor speed. So a 2GHz chip has a 500MHz bus. But that is double pumped, so it is effective 1GHz. The 1.6 GHz 970 would have an effective 800MHz bus (400x2).

Perhaps with some sort of jumper setting or whatever one can change it to 1 GHz (at least with the 2 GHz dual PPC 970) when the memory becomes available.

Last edited by Eug talking out of his ass on 06-23-2003 at 11:31 PM.

I want to say that someone over at AI mention dual channel DDR400 as being able to handle feeding a dual 970. Would that make sense (hw much "bandwidth" coudl that feed?

[3.1416]

Originally posted by power142:
I wouldn't rule out L3 on the north bridge, but an L2 cache of sufficient size and that high-speed bus could make it irrelevant.

Right. All of RAM is practically an L3.

[jcadam]

Originally posted by Scotttheking:
The 970 FSB multiplier is 4X. As the processor scales, the FSB does too.
That's why it's "up to 1ghz"

Ok, so a 2GHz 970 would have a 500MHz bus. Currently, standard DDR SDRAM does not run this fast.

I was trying to say that, perhaps the memory bus runs slower than the processor FSB. Unless Apple decided to use RAMBUS. But the specs say DDR SDRAM.....

[Spliffdaddy]

The SDRAM won't be running at any clockspeed over 200MHz. That's a fact. You can do some tricks from that point to increase bandwidth (aka "effective frequency") , but the RAM's clockspeed will not exceed 200MHz. This is the current state of SDRAM on the retail level.


For example, this P4 shows '600MHz' FSB using SDRAM @ 150MHz.

[chrisutley]

Originally posted by D'Espice:
Wrong wrong wrong.

Translation: I'm smart, you're dumb.

[Eug]

The SDRAM won't be running at any clockspeed over 200MHz. That's a fact. You can do some tricks from that point to increase bandwidth (aka "effective frequency") , but the RAM's clockspeed will not exceed 200MHz. This is the current state of SDRAM on the retail level.


For example, this P4 shows '600MHz' FSB using SDRAM @ 150MHz.

Yeah, but I'll point out to the others that that's not the point. DDR is just that. It's double the data for the clock speed. Literally. (This does not apply for the G4, since the G4 cannot make use of the extra bandwidth.)

Now dual channel is a different situation.

I am not sure what you are saying by 250x2 dual channel (do you mean you think it is 250MHz quad pumped?)

See above. Spliff is right in that the machines will likely ship with 200 MHz RAM, double pumped, in parallel, for dual channel.

ie. 200 x 2 x 2 (sort of) = 800. They'd use 250 x 2 x 2 if they could, but the memory can't be purchased (at least not in large volumes).

[Spliffdaddy]

Hopefully, the RAM will be a type that is commonly available (ie, DDR400 184pin) - else Apple is gonna have the market cornered and will, undoubtedly, charge big money for their proprietary (185pin?, lol) RAM.

Don't get me wrong...you CAN get RAM that exceeds 200MHz. Every decent video card has it. It ain't cheap and the required controller chipset would likely be a custom-manufactured piece that comes with a high pricetag.

You hafta figure that Apple will use common parts made to published and agreed specifications - wherever possible. For example, they won't spend an extra $375 per chipset per unit just to incorporate RAM that runs at 250MHz when currently available 200MHz technology is dirt cheap.

Nope. You can predict almost exactly what the specs of the next PowerMac will be based historical precedent, common sense, and cost/performance.

edited to add:

it'll look a lot like this ASUS P4PE

[CIA]

Regardless of the final tech specs...
I think we can ALL can agree that FINALLY we can say that our motherboards outpace certain technologies. I can't remember a time that Apple's motherboards weren't crippled by a slow bus, or RAM, etc....

[awcopus]

Am I missing something or do I have it?

There are two 2GHz chips in the high end machine.

A single 2GHz chip would run optimally with an FSB running at 1GHz, but there are two such chips, so Apple will include two FSBs, one per chip, right? Each 2GHz chip gets an effective FSB of 1 GHz (via these 500MHz DDR chips). It's not like each 2GHz chip will split a single 500MHz DDR FSB, right?

[Scotttheking]

Originally posted by awcopus:
Am I missing something or do I have it?

There are two 2GHz chips in the high end machine.

A single 2GHz chip would run optimally with an FSB running at 1GHz, but there are two such chips, so Apple will include two FSBs, one per chip, right? Each 2GHz chip gets an effective FSB of 1 GHz (via these 500MHz DDR chips). It's not like each 2GHz chip will split a single 500MHz DDR FSB, right?

Each chip has it's own FSB.

[D'Espice]

Yes, every processor has its own bus yet all available microprocessors have to share one single memory controller.
Other than the AMD Athlon64 CPU (aka the AMD Opteron), the IBM PPC970 does not have an on-die memory controller which means that it has to be part of the Northbridge, hence it's one single memory controller for all available microprocessors which may decrease performance big time. Actually the on-die memory controller is the biggest improvement of AMD's x86-64 architecture (actually it's not part of the x86-64 architecture itself but part of the Athlon64/Opteron architecture) therefore it would be awesome for the PowerPC970 to have something similar.

And since RAM will probably be DDR400/PC3200 (PC3700 is not JEDEC-standard yet and I highly doubt Apple is going to use something that does not have a JEDEC authorization yet) and two microprocessors might have to share this bandwith, it might turn out to be some kind of a bottleneck.

[awcopus]

"A bottleneck, but the dual 2GHz won't be crippled by it," he told himself as he gave the last 4 digits of his credit card to {vendor x} and prepared to wait for {God, how long?} until his first dual processor Mac would arrive.

Hope it isn't too much more than $3000. After all, Apple is supposed to be saving money by going with IBM's chipset, right?



So funny how I've made so many decisions and Jobs hasn't even started talking yet and I haven't even seen the thing I'm going to be buying at what cost? Which raises the question: "Does Jobs create a reality distortion field, or does he simply channel the reality distortion capacities within each of us?"

Is it June 23rd yet?