Apple has released a preliminary developer spec sheet http://developer.apple.com/documenta...PowerMacG5.pdf
This is an excerpt regarding the AGP slot:
Accelerated Graphics Port Bus
The accelerated graphics port (AGP 8x Pro) bus is a 266/533 MHz, 32-bit bus
connecting the AGP card to the U3 IC. DDR data is transmitted at both edges of the
clock for peak transfers of 2.1 GBps.
The AGP bus is an enhanced PCI bus with extra functionality to burst texture data
and other graphics across the port up to 8 times faster than a 66 MHz PCI port. The
Power Mac G5 computer’s AGP implementation is compatible with version 3 of the
AGP specification and with the Pro version of AGP. AGP 3.0 enables deeply
pipelined memory read and write operations and demultiplexing of address and
data on the bus.
To further improve the performance of the AGP bus, the U3 IC supports a graphics
address remapping table (GART). Because the virtual memory system organizes
main memory as randomly distributed 4 KB pages, DMA transactions for more
than 4 KB of data must perform scatter-gather operations. To avoid this necessity
for AGP transactions, the GART is used by the AGP bridge in the U3 to translate a
linear address space for AGP transactions into physical addresses in main memory.
For more information on the graphics cards installed in the AGP slot, refer to
“Graphics Cards” (page 33).
Note: The AGP bus is 1.5 V only and is not backward compatible. Older AGP
cards will not work in the Power Mac G5 computer.