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Catfish_Man · Jul 13, 2004, 01:34 PM

Code:
SPEC CPU2000
                    L1 I/D  L2/L3       Int           FP
Model   #CPUs MHz   (KB)    (MB)    peak   base   peak   base 
*p5-520 P5/1  1650  64/32   1.9/36    --     --  2,138  2,034
*p5-550 P5/1  1650  64/32   1.9/36    --     --  2,221  2,121
*p5-570 P5/1  1900  64/32   1.9/36    --     --  2,702  2,576

Looks like we have a new SPECfp performance king... and hopefully any POWER5 derivatives used in Macs will see similar improvements.

reader50 · Jul 13, 2004, 02:46 PM

Link, please? We trust you fully of course, but a link makes it look more official.

Eug Wanker · Jul 13, 2004, 03:51 PM

Originally posted by reader50:
Link, please? We trust you fully of course, but a link makes it look more official.

The published benches are here (PDF). (Also, check my sig.)

Commodus · Jul 13, 2004, 03:53 PM

One of the interesting tidbits I've heard is that the POWER5, due to the 90 nm process, 'only' takes up as much die space as an Opteron does (I don't know if this includes a full 36 MB of L3 cache, mind you). This is compared to the frequently huge POWER4 chips. While I doubt that Apple will start using the POWER5 in PowerMacs or Xserves (you wouldn't want PowerMacs starting at $2999), it bodes very well for the scaled-down chips that will eventually arrive.

Catfish_Man · Jul 13, 2004, 06:02 PM

Originally posted by Commodus:
One of the interesting tidbits I've heard is that the POWER5, due to the 90 nm process, 'only' takes up as much die space as an Opteron does (I don't know if this includes a full 36 MB of L3 cache, mind you). This is compared to the frequently huge POWER4 chips. While I doubt that Apple will start using the POWER5 in PowerMacs or Xserves (you wouldn't want PowerMacs starting at $2999), it bodes very well for the scaled-down chips that will eventually arrive.

The L3 cache is off-chip, but I agree that it's promising.

hmurchison2001 · Jul 13, 2004, 07:43 PM

Hubba Hubba!

Surprising there are no Int specs yet but I'm loving what I'm seeing
here. If the derivative G5 keeps that heady fp performance we'll be looking pretty damn good by summer 2005 with a new OS and kickass CPU running it. Give me SMT too please.

Catfish_Man · Jul 13, 2004, 08:52 PM

Originally posted by hmurchison2001:
Hubba Hubba!

Surprising there are no Int specs yet but I'm loving what I'm seeing
here. If the derivative G5 keeps that heady fp performance we'll be looking pretty damn good by summer 2005 with a new OS and kickass CPU running it. Give me SMT too please.

POWER5 has SMT, and 10.4 supports it (compare the hardware section of the output of sysctl -a under 10.3 and 10.4), so I can't see a POWER5 derivative happening without SMT support. As for the SPECint scores, I'm guessing they aren't quite as impressive. Some of the people at realworldtech.com are speculating ~1600 (still not too shabby though).

OreoCookie · Jul 13, 2004, 09:52 PM

AFAIK HT is not too difficult to implement if you treat the virtual CPUs as `regular CPUs'. Some OSs try to treat the virtual CPUs differently to increase performance.

Catfish_Man · Jul 13, 2004, 11:13 PM

Originally posted by OreoCookie:
AFAIK HT is not too difficult to implement if you treat the virtual CPUs as `regular CPUs'. Some OSs try to treat the virtual CPUs differently to increase performance.

Well if you treat them like regular CPUs, then it doesn't require any code at all over normal SMP support, afaik. 10.4 seems to make a distinction between logical and physical CPUs (in sysctl, anyway).

OreoCookie · Jul 14, 2004, 12:02 AM

Originally posted by Catfish_Man:
Well if you treat them like regular CPUs, then it doesn't require any code at all over normal SMP support, afaik. 10.4 seems to make a distinction between logical and physical CPUs (in sysctl, anyway).

The code needs minor adjustments to handle interrupts correctly and to be able to switch it off. The `number of CPUs' probably has to be adjusted as well.

About DragonFly and FreeBSD SMP.