A 512k 1:1 cache would indeed be very nice, but not at the expense of the L3. With a 133 MHz, or at best 167 MHz bus the G4 is starved almost beyond hope. Hence the need for the large, elaborate, multi-layered cache structure. I think if Apple told you how much of a performance difference it makes, and how much extra cost it adds to the machine, you'd agree it's a good design decision.