[P]

This is probably the best summary of Intel’s latest presentation that I have found:

https://www.anandtech.com/show/13699...ure-hybrid-x86

The TL;DR is
* New core design has a name, for some reason - Sunny Cove. It goes wider in the back (from 8 execution ports to 10) and the middle (from 4 ROB issues to 5) and in the caches.
* New special instructions for compression, crypto, and AI
* Bigger integrated GPU that looks a lot like an AMD design - no surprise given who made it. From 24 CU in the regular IGP and 48 in the upgraded to 64 CU in the model they showed. From all appearances this is the regular, GT2 version and there might be something bigger, but we don’t know that.
* These things put together is still called Icelake. There was some confusion on this.
* Icelake-U was present in silicon and running. It had mighty big coolers for what supposed to be a laptop chip, but it was in 10nm silicon and not as a PowerPoint.
* Discrete graphics are coming, called XE. OK, I guess.
* “Foveros” is Intel’s new chip stacking. EMIB gen 2, more or less. Notable that one of the tech demos had a single Sunny Cove core and 4 Atom cores. Yes heterogeneous multiprocessing, no Atom isn’t in-order anymore. Still only ARM that does that.
* Intel has changed its working process to make sure that the 10nm disaster doesn’t happen again. If something similar happens, they will put architectural improvements on the current node in the future. No real answer to why they didn’t do this already.

[reader50]

Not much mentioned about plugging the side-channel cache leaks. If they increase the cache sizes enough, high-privilege threads (like the kernel) might be assigned dedicated cache space. Less efficient use of cache, but such a thread would be completely protected.

A 3rd discrete graphics competitor would be good. It's been too long since 3dfx and matrox bowed out. Plus we still have some lingering high prices from the mining boom.

[P]

They didn’t talk about the side channel stuff this time, but they have plugged the holes that have been discovered so far. Cascade Lake, the Xeon that comes out before Icelake, has the fixes implemented like in the table on his page:

https://www.anandtech.com/show/13239...f-cascade-lake

I don’t think you can ever move fixes described as OS/VMM into hardware, so it is only the newish variant 3a (which wasn’t in the original paper, but is a variant of Meltdown) that can be moved into hardware.

[OreoCookie]

It is important to keep in mind that the relevant players know about these exploits months in advance. A very good friend of mine worked on a “popular hypervisor”, and he knew about Spectre, Meltdown and a few others he wasn't yet allowed to talk about more than half a year before they were made public. So Intel definitely did its homework on all disclosed and as-of-yet undisclosed security flaws.

Intel is playing catch-up on most of the important things, and it now depends on how well it is able to execute. Its own heterogeneous multiprocessing solution certainly sounds like great news, but now the question is what products it will release. Will e. g. Y-series chips use it? What about higher-TDP versions?

[OreoCookie]

Originally Posted by reader50 

A 3rd discrete graphics competitor would be good. It's been too long since 3dfx and matrox bowed out. Plus we still have some lingering high prices from the mining boom.

Agreed. Plus, there is a whole compute story that has definitely steered GPU design in a different direction. The prices for pro-level compute cards are still insane*, so Intel could still make some money here if they can manage to compete quickly. On the other hand, if you are interested in compute power, machine-learning optimized co-processors are the new big thing in town. Even in experimental physics, applying machine learning to analyze data has become par for the course now (I attended a conference Monday and Tuesday).

* Here in Japan it is of the order of $10,000 per card.

[P]

The heterogeneous MP solution that they showed was just a demo, but they mentioned that it was made for someone who wanted a very-low standby power state. I honestly think that it was the easiest thing they could do, and trying to integrate a GPU would be harder.

Because that is where I think this is going. I think that the 64 EU per slice GPU is going to be the mainstream model, but that there won’t be a 2 or 3 slice model like there is today. If you want that, Intel has this nice package with a small discrete GPU to sell you.

I’m also interested in the latencies again, and where the memory controller sits. Intel notably said that the PCH was in the interposer itself, but didn’t say where the memory controller sits.

[OreoCookie]

Agreed. Intel just announced technologies now and not products, which makes it hard to judge what products would look like. A while back you identified EMIB for Intel (and similar technologies for other manufacturers) as a huge deal, and I think this shows you were correct. I only really got it when I saw what AMD was doing with Rome, to be honest, but now Intel has to show what products it can build from that. It’d be interesting if Intel also chose different manufacturing processes for different bits and the like.

Now we have to wait for a year to see what products Intel will actually build, because for us consumers what matters is what chips Intel does build with it rather than could build with it. For example, it seems that Intel thinks of the big.LITTLE configuration as a solution for systems that need ultra low standby power, whereas I think this would be useful to any mobile computer. I have a grant that runs until 2020, and my current machines is almost 4 years old. So if Intel releases some good chips and Apple uses them, I’d upgrade my main machine from my left-over grant money.