[jeronimo]

Ok, now I'm lost.
What's the deal with the cache levels on the new G4s? They don't say how big is the L1. L2 is only 256K and L3 (?!) is 2Mb right? Can someone explain me please, how it works?

[THT]

The MPC 7450 has the following cache levels:

32 Kbyte of L1 instruction cache and 32 Kbyte of L1 data cache on the CPU die itself. It operates at the CPU clock rate.

256 Kbyte of L2 cache (for both data and instructions) on the CPU die itself with a 256 bit wide path to the L1 caches. It operates at the CPU clock rate.

It can support 1 or 2 Mbyte of backside cache which is the L3 cache and is off the CPU die. The backside cache controller and tags are on the CPU die itself. The backside cache bus is 64 bit, operates at various cpu-to-backside bus clock ratios, and supports DDR signaling and DDR SRAM.

I believe the 800/867 MHz Quicksilver Macs do indeed use DDR SRAM at 1:4 clock ratios. The 733 MHz Quicksilver Mac does not have L3 cache.

[Treebeard]

Originally posted by jeronimo:
<STRONG>Ok, now I'm lost.
What's the deal with the cache levels on the new G4s? They don't say how big is the L1. L2 is only 256K and L3 (?!) is 2Mb right? Can someone explain me please, how it works?</STRONG>

The L1 cache I believe is 64K on-die full processor speed. L2 is on-chip at full processor speed. (Don't ask me the difference.) L3 is 2MB (backside, I believe) at 1/4 processor speed for both the 867 and 800DP. The current QuickSilver 733 lacks an L3 cache, which apparently slows it down quite a bit.

The L3 cache was added to the PPC 7450 to make sure that the performance didn't suffer too much because of the longer 7-stage pipeline (compared to the 7400 and 7410, which had 4-stage pipelines). Longer pipelines allow for increased MHz rating (P4 has a 20-stage pipeline), but slow down the processor in the real world. The pipeline has to be loaded up, but if the processor puts the wrong data in the pipes, it has to clear them out and start over. With a relatively fast L3 cache right next to the chip, the processor just retrieves the data from that, rather from main memory which takes much longer.

Hope that helps.

[rogerkylin]

Any idea what the price difference is between the 733 with L3 and the 733 without L3?

[The Ancient One]

Any idea what the price difference is between the 733 with L3 and the 733 without L3?

The single 733 with Superdrive was $3,499 before MWNY ($2,999 with a CD-RW) and was considered the top of the line. These had 1MB of L3 cache. The single 733 is now the BOTTOM of the line and goes for $1,699 with no L3. I imagine the older machines will be available at a substantial discount for a short time. If you really need the cache, though, take a look at the single 867 with Superdrive and 2MB L3 for $2,499. You can get it built to order for a lot less if you don't need the Superdrive - a combo DVD-CD-RW drive is available for $250 less and a plain CD-RW is $400 off.

[jeronimo]

So what you guys are telling me is that the new 733 does not have L3. So it only has 256K on L2?!?! That's impressing me... I'm not an expert, but it doesn't sound good to me.

[The Ancient One]

Not exactly. Much of the software out there will not benefit significantly from the L3 cache. Whether you really need the cache or not will depend on the software you normally run. I don't know what the impact of L3 cache on OS X 10.1 and later versions will be, however. I guess we'll just have to wait for benchmarks.

[Randycat2001]

To add, the impact of L3 cache will have less effect as processor clock speeds continue to outstrip the L3 cache speeds. At 1/4 and 1/3 speeds, these outboard caches aren't that much faster than just going to main memory, considering the processor is clocking at 700+ speeds. When and if economic obstacles allow large outboard caches running at 1/2 speed and greater, then we will see a renewed emphasis on performance impacts of this cache. (This is all my opinion, of course. ) The conspiracy theorist in me suspects that L3 caches are important for performance when they can be implemented at adequate speed and size, but they are being downplayed by hardware marketing lately. Right now, large L3 caches are possible, but only at limited speed w/o blowing a pricepoint. ...Or fast cache can be used, but only at limited size w/o blowing a pricepoint. We need both (speed and size) to really make a performance impact. As it sits now, we are faced with a lesser evils situation in order to hit the pricepoint, unfortunately- either an undersized full-speed cache or a speed-bottlenecked, full-size cache. Hardware marketing tactics would have us believe that 256 KB of cache is "just fine" as long as it is full-speed when maybe it is "just OK" (mind you, still my own commentary)- certainly just barely adequate to keep these wonderful 733, 800, and 866 processors from starving outright. That's what will have to pass for now because the market hasn't any other cost-effective solution to offer for the time being.

Somebody needs to come up with a cheap, interleaved video memory chipset that can be used as a large, high-speed cache, maybe? Perhaps, nVidia could come up with something? (I dunno, maybe something like a 220 MHz, 32-MB SRAM module quad-interleaved to yield 8 MB of cache running at an effective 880 Mhz speed? Could this work, or am I on some high-test crack?) Until then, we are only enjoying a false sense of progress with these new high-clocked G4 chips (end of speculation).

[jeronimo]

Ok guys, maybe I'm not beign clear. Let's think about all the G4s...they used to have 1Mb L2 until the Megabit Ethernet version right? So how better is having 256K at 733 than 1Mb at 250 (where the old L2s at 1/2 or full speed?)?

[Nimisys]

the previous had to have been off die at 1/2 to 1/4 clock.. so the onboard stuff while less will still be faster

as for that other cache i believe micron was making some nioice about one a while back... but i don't have anymore info on it, sorry.

[blakespot]

It's worth noting that the 1/4 clock L3 cache in the new G4's (867 and dual-800) use DDR cache memory (confirmed by Mike Breeden @ XLR8YourMac.com). This means that, for ex, the dual-800's "200MHz" 1/4 clock cache runs, effectively, at 400MHz (what with DDR's ability to access the memory on both edges of the clock pulse).

Worth considering.

blakespot

[Randycat2001]

I was noting this as well. My question to that is that if this 200 Mhz cache is running as DDR, does this really give the same kind of performance as a cache that runs natively at 400 Mhz? I know that the bandwidth would improve as you would expect for a DDR scheme, but latency might still be a problem. Since the whole point of a cache is to enable memory accesses with extremely low latency (relative to going to main memory), then DDR latency may make the whole thing be a wash (but it sounds assuring in the marketing hype area). You get the benefits of increased bandwidth to a sizeable cache (where a conventional 1/4 speed cache might be bottlenecking), but latency ruins it for where a cache really would benefit you in the first place- fast access. I have heard that DDR does have its latency issues (not nearly as bad as Rambus, however), so that is why I am concerned. Do I understand it correctly that the DDR cache maintains the latency of a cache at the base 200 Mhz speed? That's not good considering that it must feed a processor making (or attempting to make, in this case) numerous memory calls at a rate of 733+ Mhz.

So I guess it's 3 factors here before things really work- bandwidth, cache size, and low latency. It's good to have any 2 of the 3 if you can get it, but it doesn't work like it should until you have all 3. The conventional 1/4 speed cache has size covered, the 1/4 speed DDR cache has size and bandwidth covered, the FSB on-die cache has bandwidth and low latency covered, but none of these choices has all 3 covered.