[moki]

Originally posted by Codename:
Ha! The Pentium 4 at 2.8GHz already beats the top of the line 1.8GHz PPC970 at SPECint and is only 100 points behind in SPECfp.

There's no way this thing will be able to beat a 4GHz P4 with SMT next year at only 1.8GHz.

Hopefully, when Jobs talked about "having options" a few months back, he was thinking of Marklar.

I'm sorry, but what benchmarks are you looking at? According to the official SPEC home page, the 2.8ghz P4 is *not* faster than the PPC970's estimated specs.

As for Marklar, that certainly is an option.

[El Pre$idente]

Originally posted by moki:
Looks pretty tasty to me -- and given the number of transistors, the move to a .9 process, this puppy has legs as well...

GP-UL Est. SPEC INT 937 @ 1.8 GHz
GP-UL Est. SPEC FP 1051 @ 1.8 GHz

from: the presentation at the MPF

Intel P4 SPEC INT 833 @ 2.4GHz
Intel P4 SPEC FP 812 @ 2.4GHz

Intel P4 Xeon SPEC INT 921 @ 2.8GHz
Intel P4 Xeon SPEC FP 878 @ 2.8GHz

from: http://www.spec.org/osg/cpu2000/results/res2002q3/

The Opteron beats all those and is real silicon (unlike the GP-UL).

http://www.theregister.co.uk/content/3/27621.html

'The 970 smokes today's desktop competition in terms of raw number crunching. By way of contrast, AMD told us today that when Opteron debuts in the first half of next year it will ratchet up a SPECint of 1202 and a SPECfp of 1170. These, AMD's John Crank told us, were based on real silicon. Nothing stands still in this business.'

[moki]

Originally posted by El Pre$idente:
'The 970 smokes today's desktop competition in terms of raw number crunching. By way of contrast, AMD told us today that when Opteron debuts in the first half of next year it will ratchet up a SPECint of 1202 and a SPECfp of 1170. These, AMD's John Crank told us, were based on real silicon. Nothing stands still in this business.'

Actually, if you want to realistic about it, the Itanium2 is the current benchmark king -- even at just 1ghz. Too bad the chips cost $3,000 or so a pop.

http://www.theinquirer.net/?article=4266

But that is neither here nor there. The fact is that the PPC970 is quite a leap in terms of performance, and it includes Altivec, has a killer bus speed, and will scale extremely well. This is the ground floor for the PPC970 -- chips like the P4 are in their upper range.

[Graymalkin]

D'Espice: Stop spouting CISC crap about the newer Pentiums, since the Pentium Pro Intel's chips have had RISC-like cores and x86 instruction translation. The only thing CISC on any recent Pentiums is the instruction set. The main difference between PPro derivitives and real RISC chips is the number of registers, pentiums have a fraction of the registers most modern RISC chips have.

x86 emulation on PowerPC is also not due to a problem with the PowerPC chips but instead with the translation required to work with x86 instructions. PowerPC chips have fixed length instructions and are able to do decode and dispatch operations on the same cycle, it isn't so easy when you're translating an x86 translation. Ergo your instruction throughput drops. The only thing that makes Pentiums and Athlons run with any modicum of speed is the intensive instruction decode units and micro-op caches.

Scott: The GPUL is being designed to run on Apple's new processor interconnect that is set to replace MaxBus (finally). From various articles floating around this will be called ApplePI. Given the sort of technologies the GPUL is bringing over from the POWER4 this new interconnect scheme will probably point to point communication between the processor and memory controller. A little memory pre-fetch like whats in the nVidia nForce would make it quite a badass.


Also I've seen mentioned that Apple is indeed going for the Motorola 7555 in the first half of 2003. This is where things get confusing. IBM fully admitted Apple is going to be using the GPUL when it is released, they're also going to release Linux based systems themselves running on this chip. Then Apple is deciding before that they are going to hop onto Motorola's gravy train again using the 7555. I'm only guessing at the 7555's specs but I'm thinking an e500 core with an AltiVec unit strapped to its back and a non-integrated memory controller. IIRC the e500 core is only dual issue superscalar where the G4 is four issue, maybe Mot's got a different or improved core with better capabilities. Then again the 7555 could merely be a renamed 7455 with some enhancements to the memory interface or something. It's hard to find anything useful regarding the chip because there's still so much flotsam over the 85xx chips. The Register pointed at MOSR and MOSR pointed at the Register and none of those jackasses knew what they were talking about. Now reporters are mentioning Apple confirming a move to a "7555" chip from Motorola.

The lack of hard facts is a bit annoying, you can look up the SPEC performance of a chip from IBM still a year away but a processor Motorola is supposedly going to roll out in a couple months is a complete mystery. Anyone want to point out something meaningful (notm entioning a Register, Geek.com, or MOSR article) concerning the 7555?

[gumby5647]

ok, So the PowerPC 970 is going to start out with 512k of L2 on a .13micron process.


So, how much L2 could they squeeze on there when it shrinks to .09microns?

[Graymalkin]

Originally posted by gumby5647:
ok, So the PowerPC 970 is going to start out with 512k of L2 on a .13micron process.


So, how much L2 could they squeeze on there when it shrinks to .09microns?

A lot. The problem with L2 cache is it needs to be fast, it is expensive to make a large fast L2 cache. One of the reasons high end chips like the PA-RISC 8600 and POWER4 cost so much is the amount of L2 cache they run at either core clock or half core clock. As your clock speed increases the latency of the memory becomes more of a problem. At 90nm they could potentially get a bunch of L2 cache but it might not be economical to do so. The most they'd probably be able to put on a 2GHz version of the chip would likely only be 1MB.

[dru]

Originally posted by Codename:
Ha! The Pentium 4 at 2.8GHz already beats the top of the line 1.8GHz PPC970 at SPECint and is only 100 points behind in SPECfp.

There's no way this thing will be able to beat a 4GHz P4 with SMT next year at only 1.8GHz.

Hopefully, when Jobs talked about "having options" a few months back, he was thinking of Marklar.

Why does everyone assume these (theoretical 970-based PowerMacs) won't be dual processor systems? Afterall it's designed to scale to 16-way SMP.

[moki]

Originally posted by dru:


Why does everyone assume these (theoretical 970-based PowerMacs) won't be dual processor systems? Afterall it's designed to scale to 16-way SMP.

Yeah, very true -- but people are far underestimating the power of these processors, but narrowmindedly focusing on the SPEC scores (which are quite good, btw).

Those who know their stuff about processor architectures are certainly going to have their heads turned by the PPC970...

[Scotttheking]

Ok, I've cleaned out most of the troll posts.

NOW

[Superchicken]

Might the G5 go into the Power Books and the PPC 970 go into Power Macs?
or perhaps at January 2003 or 4 have it set up

Power Mac: PPC 750

Power Book and iMac G5

iBook and eMac G4???

I dono but if Moto's still making a decent desktop chip that might be less powerful than the PPC 970 but more powerful than a G4 perhaps apple woudl have it in it's best interest to go with that one also... or they could leave moto out to dry

[BlackGriffen]

Originally posted by Superchic[k]en:
Might the G5 go into the Power Books and the PPC 970 go into Power Macs?
or perhaps at January 2003 or 4 have it set up

Power Mac: PPC 750

Power Book and iMac G5

iBook and eMac G4???

I dono but if Moto's still making a decent desktop chip that might be less powerful than the PPC 970 but more powerful than a G4 perhaps apple woudl have it in it's best interest to go with that one also... or they could leave moto out to dry

He he, he he. Chicken man is predicting the return of the G3 to the high end .

BlackGriffen

Edit: should have known I'd get type-o's in a post making fun of someone for a type-o

[709]

Well, I have to say this is the best news I've heard all decade.

Spec scores? So what. Intel & AMD as competitors? Competing with what? OSX vs MSXP? Please.

We've all hung in there thus far...and it sounds like we will be justly rewarded.

Fast/Shmast. Spec/Shmec. I'll just be happy to have one (or 2, or 16) of these babys in my next tower.

- G

[edit] [Those who know their stuff about processor architectures are certainly going to have their heads turned by the PPC970...]

moki, I don't know a damn thing about processors, but my head is spinning like Linda Blair.

[KidRed]

Not sure if this is big news or not, but the 970 has 2 SIMD units. Isn't that very good news? And if that's on one chip and we get a dual that means 4 SIMD units. That sounds good to me, maybe someone can elaborate on the significance of this?

[moki]

Originally posted by KidRed:
Not sure if this is big news or not, but the 970 has 2 SIMD units. Isn't that very good news? And if that's on one chip and we get a dual that means 4 SIMD units. That sounds good to me, maybe someone can elaborate on the significance of this?

It means that two altivec instructions can be decoded and executed in parallel -- so well coded altivec routines instead of being 10x or so faster than normal will end up being 18-20x faster than normal.

There is a lot to love on this chip, there really is -- the bandwidth from the CPU to memory controller is just absolutely stunning -- low transistor count -- a quick move to .9 process -- 16 way SMP -- yummy.

In terms of a complete package, the performance of this beast should be quite stellar -- let alone if Apple decides to make dual processor configurations. Yowza.

[icknay]

Check out the nice review by David T Wang at Real World Tech...

http://www.realworldtech.com/page.cf...WT101502203725

Apparently the pipeline is 14-22 stages long, which suggests the chip should scale similarly to the P4. Also, the CPU bus is a little exotic -- Apple will need to be on the ball to get the Northbridge right, and multiprocessor setups will require extfa work.

[709]

OK Then. I've bought nothing but duals since the highly celebrated DP533. So, given Apple's push towards an all DP lineup, do you think they will continue with this new chip?

-G

( Not wanting to break NDAs or anything, just your insight)

[file]

Originally posted by moki:

In terms of a complete package, the performance of this beast should be quite stellar -- let alone if Apple decides to make dual processor configurations. Yowza.

and when you drool...dont forget that when you get this machine, you'll be getting it with OSX and it's improvements a year from now.

i hope they continue with Quartz Extreme and it's latest incarnation as well. (anybody know if QE is effected by this new chip in any way?)

[709]

Originally posted by file:


and when you drool...dont forget that when you get this machine, you'll be getting it with OSX and it's improvements a year from now.

i hope they continue with Quartz Extreme and it's latest incarnation as well. (anybody know if QE is effected by this new chip in any way?)

Let's hope so. Or at least maybe with this chip they won't have push so much through the GPU. Even on my DP1Ghz it stills feels a bit sluggish.

-G

[Scotttheking]

It looks like I got my answer regarding SMT.

http://www.iseriesnetwork.com/resour...ontentID=15238

IBM is adding it to the Power5, so it will not be in the GPUL, but it will come.

Another new feature in POWER5 will be simultaneous multithreading (SMT). The idea behind SMT is to share the processor hardware on a chip among multiple threads in a multiprogrammed workload. In this way, a single processor on the chip can sometimes act as two processors.

[moki]

Originally posted by Scotttheking:
It looks like I got my answer regarding SMT.

http://www.iseriesnetwork.com/resour...ontentID=15238

IBM is adding it to the Power5, so it will not be in the GPUL, but it will come.

SMT makes even more sense in processors like the POWER4 and presumably the POWER5 (compared to the Pentium), because of their dual core nature.

[BlackGriffen]

Does IBM have a conflict of interest here? I mean, did they perhaps make this chip a little less stellar than they could have in order to avoid competition between it and the POWER line of high end procs?

BlackGriffen

[raskol]

Originally posted by BlackGriffen:
Does IBM have a conflict of interest here? I mean, did they perhaps make this chip a little less stellar than they could have in order to avoid competition between it and the POWER line of high end procs?

BlackGriffen

I am sure the differences between the Power4 and the PowerPC 970 all have to do with the price point of the chips. The Power4 is used in extremely expensive servers. The 970 is a desktop CPU. Not many are willing to pay $10,000 for a desktop Mac. Do you have any idea how much 64MB of 900Mhz cache RAM costs? I don't either. There is nothing wrong with this CPU. Why is everyone so negative?

[D'Espice]

Originally posted by Graymalkin:
D'Espice: Stop spouting CISC crap about the newer Pentiums, since the Pentium Pro Intel's chips have had RISC-like cores and x86 instruction translation. The only thing CISC on any recent Pentiums is the instruction set. The main difference between PPro derivitives and real RISC chips is the number of registers, pentiums have a fraction of the registers most modern RISC chips have.

x86 emulation on PowerPC is also not due to a problem with the PowerPC chips but instead with the translation required to work with x86 instructions. PowerPC chips have fixed length instructions and are able to do decode and dispatch operations on the same cycle, it isn't so easy when you're translating an x86 translation. Ergo your instruction throughput drops. The only thing that makes Pentiums and Athlons run with any modicum of speed is the intensive instruction decode units and micro-op caches.

You are absolutely right. From an architecture perspective, the x86 CPUs, beginning with the 6x86 (PPro), behave like RISC-based microprocessors by decoding the complex x86 instructions into short RISC-like �Ops.
Yet, from a software perspective, they are still pure CISC microprocessors with a viarable instruction length and a complex instruction set. And when talking about using a different architecture for future computers, you have to look at the whole thing from the software perspective rather than the architecture perspective.
I hope you understand what I mean, it's not that easy to explain. Basically, what I'm trying to say is, that from an architecture perspective you are absolutely right and I would be either insane or unillumined if I'd disagree with you. However, from a software perspecitve I am right by saying that they are completely different, CISC-based microprocessors, know what I mean?

Also, again from my perspective, the instruction sets are all but compatible...

[KidRed]

Originally posted by file:


and when you drool...dont forget that when you get this machine, you'll be getting it with OSX and it's improvements a year from now.

i hope they continue with Quartz Extreme and it's latest incarnation as well. (anybody know if QE is effected by this new chip in any way?)

We might also, have ATIs All-In-One or at least the cards will be that much better

[moki]

Originally posted by BlackGriffen:
Does IBM have a conflict of interest here? I mean, did they perhaps make this chip a little less stellar than they could have in order to avoid competition between it and the POWER line of high end procs?

BlackGriffen

No, they don't. Some speed sacrifices were made for the POWER4 chip in order to maintain an exceedingly low failure rate in the chip -- it is focused on a different market, with different concerns.

Additionally, IBM is already hard at work on the POWER5 and POWER6 architectures....

[Graymalkin]

Originally posted by D'Espice:

You are absolutely right. From an architecture perspective, the x86 CPUs, beginning with the 6x86 (PPro), behave like RISC-based microprocessors by decoding the complex x86 instructions into short RISC-like �Ops.
Yet, from a software perspective, they are still pure CISC microprocessors with a viarable instruction length and a complex instruction set. And when talking about using a different architecture for future computers, you have to look at the whole thing from the software perspective rather than the architecture perspective.
I hope you understand what I mean, it's not that easy to explain. Basically, what I'm trying to say is, that from an architecture perspective you are absolutely right and I would be either insane or unillumined if I'd disagree with you. However, from a software perspecitve I am right by saying that they are completely different, CISC-based microprocessors, know what I mean?

Also, again from my perspective, the instruction sets are all but compatible...

From a software perspective I'm not really sure what you're talking about. The only people that really interface with a given ISA's instructions are compiler writers. The difference between x86 and PPC is academic when you're writing anything in a high level language.

[CIA]

Super early for this but.... Any idea's about price in quantity? What do the current Moto G4's cost?

[Metzen]

Originally posted by moki:
It means that two altivec instructions can be decoded and executed in parallel -- so well coded altivec routines instead of being 10x or so faster than normal will end up being 18-20x faster than normal.

There is a lot to love on this chip, there really is -- the bandwidth from the CPU to memory controller is just absolutely stunning -- low transistor count -- a quick move to .9 process -- 16 way SMP -- yummy.

In terms of a complete package, the performance of this beast should be quite stellar -- let alone if Apple decides to make dual processor configurations. Yowza.

Errr... Not to breach anyones bubble here regarding AltiVec/Velocity Engine/VMX/VRF or whatever it's called by IBM, but if the PPC 970 only achieves 18MKey's at RC5 using a 1.8Ghz proc... Well... The G4's AltiVec unit would scale (theoretically) the same as well. (22MKey's at 1.25Ghz / 2 (for Dualies) = 11MKeys @ 1.25Ghz per proc * 1.44 (Mhz descripency) = approx. 1.6MKeys)

What I'm getting at, is it appears you either need to rewrite your software to take advantage of the 2nd AltiVec unit or (hopefully) just recompile.

Anyways, this is all under the assumption RC5 is a good-well coded AltiVec application (which I think it is).

And now for gloating points:

Originally posted by Metzen:
L1 Cache: 96Kb As I seem to recall, this was one of the major reasons the Athlon was so speedy; the large amount of L1 Cache. The amount listed here doesn't match the amount of L1 cache on the Athlon (128Kb), but interestingly enough, IBM found it well enough to increase it on the Power4.

This doesn't mean IBM won't go 32+32 for 64Kb of cache, nor is it a Power4 derived technology, but it's interesting, nonetheless.

(See Page 4 )

[razerr]

Originally posted by Codename:
By the time IBM's 1.4GHz-2.0GHz GPUL comes out, it be pittyful in comparison than Intel's 4.0GHz P4 (with hyperthreading) or AMD's 3800 rated SledgeHammer.

I would suggest you not wait and buy yourself a nice 3GHz P4 which in all probability will still be faster than Apple's offerings next year.

Wait up..

The P4 IS NOT 64 bit.
A 64 bit processor at 1.4 is insanely fast. When Intel originally put out the itanium it started at sub gigahertz speed. Intel started trying to combat the MHz myth as well.

[D'Espice]

Originally posted by Graymalkin:


From a software perspective I'm not really sure what you're talking about. The only people that really interface with a given ISA's instructions are compiler writers. The difference between x86 and PPC is academic when you're writing anything in a high level language.

I's afraid of something like that. You're looking from a programmers/compilers perspective, and what the programmer or compiler has to pay attention to. Sure, when writing anything in a high level language like C++ or JAVA in the end the compiler makes the difference.

But now let's forget the programmers/compilers point of view for a minute, shall we? Let's look at what is not what will be. Because despite the indisputable fact that either architecture, PPC as well as x86, is RISC deep down inside (pure RISC on one side, �Ops on the other), for any existing software either architecture is different. That is what I'm talking about, so even if both CPUs are RISC deep down inside the core, they are quite differente and will remain incompatible.

[BlackGriffen]

Originally posted by D'Espice:

I's afraid of something like that. You're looking from a programmers/compilers perspective, and what the programmer or compiler has to pay attention to. Sure, when writing anything in a high level language like C++ or JAVA in the end the compiler makes the difference.

But now let's forget the programmers/compilers point of view for a minute, shall we? Let's look at what is not what will be. Because despite the indisputable fact that either architecture, PPC as well as x86, is RISC deep down inside (pure RISC on one side, �Ops on the other), for any existing software either architecture is different. That is what I'm talking about, so even if both CPUs are RISC deep down inside the core, they are quite differente and will remain incompatible.

It's interesting to note that the PPC 970 actually takes a similar approach as the Pentium IV. In the initial stages of the pipeline, there is a stage where some of the more complex PPC ops are "cracked" (IBM's terminology) in to a few smaller ops before they are passed on to the core. Here are the relevant paragraph from the initial Ars article:

The 970 fetches eight instructions per cycle from its 64KB instruction cache into an instruction queue. These instructions then move through a series of pipeline stages that IBM calls "decode, crack, and group formation." (I'll explain why these stages are so called in a moment.) From the "decode, crack, and group formation" phase, the 970 dispatches five instructions per clock (4 instructions + 1 branch) in program order to a set of issue queues. The out-of-order execution logic then pulls instructions from these issue queues out of program order to feed the chip's eight functional units.

The mechanics behind this five-issue design are fascinating, and I'll touch on them briefly here. Both the 970 and the Power4, much like the Pentium and the Athlon, convert instructions in their "native" ISA into a special internal instruction format for execution. Just like the P4 decomposes x86 instructions into smaller, simpler micro-ops (uops), the 970 "cracks" PowerPC instructions into smaller, simpler sets of "iops". It is these iops that are actually executed by the 970's functional units. Most PPC instruction decode into only one iop, but some occasionally decode into more.__

Unlike the P4, the 970 does one more trick after it has cracked the PPC instructions down into iops. The 970 divides up the iop stream into "groups" of five iops a piece. So first it cracks the PPC instructions down into iops, then it collects the iops back together into groups. The iops are placed the group's five slots in program order with the stipulation that all branch instructions must go in slot 4 (the last slot). Furthermore, slot 4 can hold only branch instructions and nothing else. It is these groups of five iops that are dispatched in-order to the issue queues. (I haven't yet seen a functional diagram of the 970's core, so I'm not sure how many issue queues there are.)

BlackGriffen

[KidRed]

Originally posted by razerr:


Wait up..

The P4 IS NOT 64 bit.
A 64 bit processor at 1.4 is insanely fast. When Intel originally put out the itanium it started at sub gigahertz speed. Intel started trying to combat the MHz myth as well.

Sinds you're new hear, I'll give some advice- Don't feed the trolls, it's dangerous.

[Superchicken]

I wonder if I could convince a troll to eat Cyanide?

[moki]

Originally posted by Metzen:


Errr... Not to breach anyones bubble here regarding AltiVec/Velocity Engine/VMX/VRF or whatever it's called by IBM, but if the PPC 970 only achieves 18MKey's at RC5 using a 1.8Ghz proc... Well... The G4's AltiVec unit would scale (theoretically) the same as well. (22MKey's at 1.25Ghz / 2 (for Dualies) = 11MKeys @ 1.25Ghz per proc * 1.44 (Mhz descripency) = approx. 1.6MKeys)

What I'm getting at, is it appears you either need to rewrite your software to take advantage of the 2nd AltiVec unit or (hopefully) just recompile.

No, you're right -- I misunderstood the information I checked out -- it isn't two entirely separate AltiVec units, but rather a two stage AltiVec unit -- so performance should be comparable to a G4 of similar clockspeed (if one existed) for AltiVec code.... which is nothing to sneeze at, btw. AltiVec remains the best SIMD implementation on the planet.

[Ken_F2]

moki,

I am sorry, but you are incorrect...

I'm sorry, but what benchmarks are you looking at? According to the official SPEC home page, the 2.8ghz P4 is *not* faster than the PPC970's estimated specs.

It seems you quoted SPEC results for a P4 with PC2100 DDR RAM. Systems are now sold with DDR333 or PC1066 RDRAM, with dual channel DDR systems coming next month. The latest SPEC result postings (with configuration info) can be found right here. Click on the "HTML" for a link to the configuration and result at Spec.org.

The current high result is for a Dell P4 2.8 with PC800 RDRAM; it scored a SPECint2000_base of 970 and a SPECfp2000_base of 938. The highest AMD score is for a new Athlon 2800+ with an Nforce2 motherboard; it scored a SPECint2000_base of 898 and a SPECfp2000_base of 782.

As for the IBM PPC 970, it is expected to score 937 on SPECint2000_base, and 1051 in SPECfp2000_base, as you can see on this IBM page. IBM did not specify whether this was for 32-bit or 64-bit mode, as best I can tell. Thus, it would appear that the next-generation PowerPC 970 processor from IBM, when it debuts in late 2003 at 1.8GHz, will offer comparable performance to a 2.8GHz to 3.0GHz P4.

AMD also announced actual SPEC scores for its forthcoming Hammer processor. According to AMD, it's Opteron at 2.0GHz (3400+) will score 1202 in SPECint2000, and 1170 in SPECfp2000--this is for 32-bit mode using the current Intel compiler, which is the compiler typically used on the x86 platform. According to AMD, the processor should score 20% higher--SPECint2000 score of 1400--in 64-bit mode. See the AMD presentation slide right here, or read the commentary from an attendee right here. This was for the Opteron with 1Mb L2 cache, while the Clawhammer desktop processor (3400+) is expected to debut with 256K L2 at a somewhat higher frequency--2166 to 2400MHz.

Intel's Itanium2 currently scores 1356 in SPECfp2000 under Linux 64, with Intel having said the next Itanium, coming in the first half of 2003, will offer 30-50% better performance (SPECfp2000 of >1800). It's not clear what the "Prescott" PentiumV will score when it becomes available in July/August of next year, but you can read more about it right here. Prescott will be built on the 90mm process, and use in excess of 100 million transistors---compared to 55 million for the current P4. Interestingly enough, the IBM 970 will sport 52 million transistors, and will be almost as large as the current P4.

[Ken_F2]

While the "megahertz myth" is currently more of a stalling tactic by Apple than anything else (although under the right circumstances, Altivec does provide a boost), it's a known fact that clock speed alone doesn't determine efficiency, and the importance of clock speed will diminish even further in the move to 64-bit chips.

This is nonsense.

With 64-bit, you get two main benefits--the ability to address RAM sizes larger than 4 gigabytes (helpful for large database servers, etc) and additional registers. The extra address space is of no benefit for typical Mac users, which won't have, need, or be able to afford 4 gigabytes of DDR RAM in their systems. Use of the additional registers with applications compiled and optimized for 64-bit can improve performance in the range of 10% to 20%; however, these additional registers are useless and inaccessible for (and under) the existing 32-bit OSX and Mac applications. Nor will a simple recompile [for 64-bit] attain the full benefit of these extra registers. There is nothing about the "64-bitness" in a processor that limits clock frequency or scaling.

Case in point: AMD's 64-bit Athlon and Opteron chips, due out in 2003. The first "Clawhammers" (as the basic CPU design has been codenamed), like the current Athlon XPs, will be given a PR (performance/Pentium rating, not public relations) rating of 3400+. What do you think the real-world clock speed will be? 2.5 GHz? 2.8? Wrong! AMD's first 64-bit chips will be clocked at 1.6 GHz, but will be rated as more than twice as fast as a similarly-clocked Pentium 4.

This is nonsense. An AMD representative confirmed some weeks ago that the 1.6GHz figure was bogus. AMD announced on Monday that the Hammer series of chips would debut at >=2.0GHz for Opteron. Hammer for the desktop (Clawhammer) is expected to debut at 2133 to 2400MHz for a 3400+ rating. AMD's announced benchmarks this week for the Opteron 3400+ at 2.0GHz that put its performance at 28% faster than the IBM 970 in integer operations for 32-bit mode (Specint2000 of 1202), and nearly 50% faster than the IBM 9700 in 64-bit mode (SPECint2000 of ~1400).

The Pentium 5 coming next year? Hellooooooo FUD. You are now labeled a Troll. Why? The P5 isn't coming till at least 2005

You are mistaken. Intel confirmed at IDF that "Prescott" would be its next-generation Pentium processor based on its "NetBurst Microarchitecture." The "NetBurst Microarchitecture" refers to the 20 pipeline design. According to Intel president Paul Otellini at the Intel Developer Conference last month, "Prescott will have so many new advanced features that it is not just another Pentium 4 processor, but a new generation of its own." See the article right here. The current P4 has 55 million transistors, while Intel announced that the "Prescott" PentiumV would feature in excess of 100 million transistors. More information on the "Prescott" PentiumV can be found on News.com, eetimes.com, and other IT news, processor and engineering related sites.

Nehalem refers to the from-scratch, from-the-ground-up processor architecture redesign; it's expected to integrate multiple cores and use a pipeline of somewhere between 21 and 30 stages, with a clock of between 6GHz and 10GHz. The information on the processor originally came from an interview with a prominent Intel engineer on Intel's site (since removed), where he talked about some of the exciting projects that he was working on. In the interview, he said he expected Nahalem to be called the Pentium 8, and to enter production in the second half of 2004.

[type_r503]

Doesn't anyone find it strange that IBM is not calling the new chip a G5, I know this is an Apple name, but all the rumors around the new Motorola chip refer to it as G5. Do you really think that the G5 is over a year away? There is no way the G4 can last another year, with apple posting a loss today, I would put my money on a G4 replacement for the Pros by early next year. And the PPC970 to replace the G4 in the consumer models in early 2004.

type r 503

[Mac The Fork]

Thus, it would appear that the next-generation PowerPC 970 processor from IBM, when it debuts in late 2003 at 1.8GHz, will offer comparable performance to a 2.8GHz to 3.0GHz P4.

It would, but that's while running SPEC, and on a system for which we don't know the details.

With 64-bit, you get two main benefits--the ability to address RAM sizes larger than 4 gigabytes (helpful for large database servers, etc) and additional registers.

You don't get additional registers; you get bigger ones. x86-64 gives you more registers, but that has nothing to do with it being a 64-bit chip.

[Metzen]

Originally posted by Ken_F2:
It's not clear what the "Prescott" PentiumV will score when it becomes available in July/August of next year, but you can read more about it right here. Prescott will be built on the 90mm process, and use in excess of 100 million transistors---compared to 55 million for the current P4. Interestingly enough, the IBM 970 will sport 52 million transistors, and will be almost as large as the current P4.

Ken_F2, look, I cited a resource stating that the "Pentium V" will not be out till 2005 at the earliest.

Read. Read it again. And again.

What are these new features of Prescott?

Let's see...

Top speed of 3.2GHz come Q2 2003...
Hyperthreading
NetBurst (read: we're trying to fix some gaping holes in that 20-stage pipeline of ours.)
And lastly:
The first carnation of Palladium in the form of La Grande.

This doesn't sound like a new chip to me. Sheesh. A little improvement yes, all new chip? No...

[Apocalypse]

First of all, it is obvious that Ken_F2 seems only slightly better than a troll. He almost knows what he is talking about but not quite enough (plus, it annoys me when anti-innovation jerks come into Mac forums). 64-bit design does not refer to the number of registers at all. In fact, it doesn't really refer to anything in particular. It is commonly used to describe the size of the general purpose integer registers on a chip and that is what we are talking about here. For example, a G4 has a 64-bit internal data path, 64-bit FP registers and 128-bit vector registers. However, we call it 32-bit since it has 32-bit ints. The number of accessible general purpose registers is something the Intel and AMD are hacking out (and might not be doing the same way, which could be an issue) but is not actually defined by the original design for x86.

Also it is worth noting that you can affect scalability of clock by increasing the number of bits used for describing instructions and storing data since you now have to run twice as many traces on the chip which can dramatically increase noise (thus killing stability, and ultimately scalability).

Carrying on, these SPEC tests only demonstrate repetitive code using general purpose registers (well, the one uses FP tests) so they are more a function of clock then anything else (although they are also impacted by the number of functional units and the number of instructions dispatched per clock). Usually we don't do well on these since they ignore the advantages of G4 CPUs (short pipe, big and fast caches, AltiVec, etc). They work as a measure, I guess, but don't forget that they were made popular by Intel pushing them as a source for benchmarks.

RISC vs CISC: As much as modern X86 are implemented as RISC (for example, you can't have a pipeline in CISC) they are still being held back by it (this is why I am annoyed that AMD is forcing Intel to abandon getting Itanium to work in the name of compatibility and getting something sooner rather than later since it was a design that didn't suck). For example, X86 compilers have to do tons of work to make up for short-comings in the instruction set while a compiler for a true RISC instruction set and register set can worry more about higher-level optimizations. This is why I wish that we could abandon it and get AMD and Intel to work on better designs since with their volume and R&D budgets we could have some damn good chips!

Finally, let us not forget that these results were acquired from "actual silicon". They have the prototypes to prove that the design actually will work, it is just that they probably have very few and won't have the process into the realm of reliability and efficiency for some time. Also, don't go around saying that it barely out-performs an Itanium or Opteron since those aren't desktop CPUs! If you want to compare those to something, look at the POWER5 specs, or something.

All in all, I am very excited about this. I can't wait!

Jeff.

[moki]

Originally posted by Ken_F2:
Thus, it would appear that the next-generation PowerPC 970 processor from IBM, when it debuts in late 2003 at 1.8GHz, will offer comparable performance to a 2.8GHz to 3.0GHz P4.

No, it would appear that the next generation PowerPX 970 processor will have comparable SPEC INT and SPEC FP performance to s 2.8-3ghz Pentium 4.

There is a WORLD of difference between "performance" and "performance on two very specific benchmarks".

You can absolutely expect the PPC970 to smoke at a number of real-world tasks, and a number of benchmarks as well. There are many folks using RS/6000 workstations today -- whose SPEC scores are significantly lower than the P4 machine you cite -- who would be quite amused if you suggested they should use a P4 because it is"faster".

[Ken_F2]

What are these new features of Prescott?

Intel is keeping them under wraps for now. I don't know why you point me to a Cnet article that relies on heresay and rumors, whereas I point you to an article with the official position and statement of Intel Corporation.

Intel essentially confirmed at IDF that "Prescott" would be called PentiumV. On Intel's own Powerpoint presentation from IDF, it says that "Prescott" will NOT use the Pentium4 name. Nowhere does that Cnet article state or imply otherwise.

Intel has said (read the link), "Prescott" is Intel's next-generation processor based on the "NetBurst Microarchitecture," which is the microarchitecture that made its debut with the Pentium4. The Pentium2 and Pentium3 were based on "P6 microarchitecture" that made its debut with the Pentium Pro. Like the Pentium2 and Pentium3, the "Prescott" PentiumV will NOT be a completely new architecture, but rather a rework of an existing architecture; it will NOT be a new processor architecture developed from scratch, which is what the Cnet article refers to in Nehalem. Some have speculated that Nehalem will be the first desktop processor to incorporate all or some of the IA64/Itanium architecture.

[Scotttheking]

Ken, enough.

This is not the P4 thread. Try ars for that.

[Metzen]

Originally posted by Ken_F2:
With 64-bit, you get two main benefits--the ability to address RAM sizes larger than 4 gigabytes (helpful for large database servers, etc) and additional registers. The extra address space is of no benefit for typical Mac users, which won't have, need, or be able to afford 4 gigabytes of DDR RAM in their systems. Use of the additional registers with applications compiled and optimized for 64-bit can improve performance in the range of 10% to 20%; however, these additional registers are useless and inaccessible for (and under) the existing 32-bit OSX and Mac applications. Nor will a simple recompile [for 64-bit] attain the full benefit of these extra registers. There is nothing about the "64-bitness" in a processor that limits clock frequency or scaling.

Something people just don't seem to get...

Why do server's love 64bit? 64bit is a huge amount of data to shuffle. By shuffling data in 64bit chunks you can carry same amount of data as 2 32bit chunks. To process an equal amount of 32bit data on a 32bit machine you have to be 2x faster minimum. It's nearly the same situation RDRAM faces vs. DDR RAM at the server level. DDR RAM, at present only operates at a bus speed of 200Mhz tops (400MHz effective) vs. RDRAM's 800MHz. Why such a disparity? DDR RAM is 64bit where as RDRAM is only 16bit. Fortunately, for RDRAM, data that "streams" (read: things like Quake or MP3 encoding where data is sent sequentially) at present doesn't need more than the space provided by that 16bit chunk of data. Applications like, web serving, database applications, 3D modeling programs, video workstations, etc. kill RDRAM because of that poor data-width, at a fraction of the speed.

Same goes for processors. And with a application working on a 64bit chunk vs. the same application working on a equal sized 32bit chunks on the same processor (this is assuming native support of a 32bit environment), you should see the 64bit portion be completed significantly faster than two smaller 32bit chunks at the same speed.

There is more to 64bit than just more RAM and "additional registers".

Originally posted by Ken_F2:
This is nonsense. An AMD representative confirmed some weeks ago that the 1.6GHz figure was bogus. AMD announced on Monday that the Hammer series of chips would debut at >=2.0GHz for Opteron.

AMD has enough problems then spewing off that they got something better to sell, when, in fact, they have next to nothing.

They are barely shipping 2400+ CPU's and 2600+ CPU's.

They continue to push back Hammer release dates, and they're adding Palladium to there processor's as well...

Forget AMD, who wants them?

Originally posted by Ken_F2:
You are mistaken. Intel confirmed at IDF that "Prescott" would be its next-generation Pentium processor based on its "NetBurst Microarchitecture." The "NetBurst Microarchitecture" refers to the 20 pipeline design. According to Intel president Paul Otellini at the Intel Developer Conference last month, "Prescott will have so many new advanced features that it is not just another Pentium 4 processor, but a new generation of its own." See the article right here. The current P4 has 55 million transistors, while Intel announced that the "Prescott" PentiumV would feature in excess of 100 million transistors. More information on the "Prescott" PentiumV can be found on News.com, eetimes.com, and other IT news, processor and engineering related sites.

I don't see Intel calling it the Pentium 5 yet:

Intel and analysts agreed that the chip represents less a complete overhaul of the Pentium architecture than a substantially improved revision... ...Exactly how much of a departure the new chip entails will likely be revealed when the company assigns Prescott a brand name, according to other analysts.

Even Intel agrees Prescott is just something to sneeze at.

Originally posted by Ken_F2:
Nehalem refers to the from-scratch, from-the-ground-up processor architecture redesign; it's expected to integrate multiple cores and use a pipeline of somewhere between 21 and 30 stages, with a clock of between 6GHz and 10GHz. The information on the processor originally came from an interview with a prominent Intel engineer on Intel's site (since removed), where he talked about some of the exciting projects that he was working on. In the interview, he said he expected Nahalem to be called the Pentium 8, and to enter production in the second half of 2004.

Pentium 8 by 2004???? HAHAHAHA!

Hahaha! Whoa, whoa, whoa... Let me guess, they are going to P5, P6 AND P7.. ALL in 2003?

HAHAHAHA! My god that's funny.

You, poor Ken_F2, young troll, and evidently, undereducated peon, will now be added to my ignore list.

Good Day!

[Metzen]

Originally posted by moki:
No, you're right -- I misunderstood the information I checked out -- it isn't two entirely separate AltiVec units, but rather a two stage AltiVec unit -- so performance should be comparable to a G4 of similar clockspeed (if one existed) for AltiVec code.... which is nothing to sneeze at, btw. AltiVec remains the best SIMD implementation on the planet.

I wasn't disagreeing with that. I'm agreeing with you there

One quick question:

I seem to recall reading that the AltiVec unit here was bumped up a bit, is the FP unit of the AltiVec chip on the current G4 running at 64bit? I thought the big issue w/most developers I know (3D peeps) is that they can't optimize for AltiVec because it doesn't do double precision (at any benefitcial speed) to the FP unit on the processor.

Anyone know if this has changed with this implementation? I thought I had read somewhere that it had.

[Ken_F2]

There is a WORLD of difference between "performance" and "performance on two very specific benchmarks".

I don't follow. IBM is expressly using these SPEC benchmarks in its MPF presentation to paint a picture of the 970's performance. If they didn't believe the SPEC score was indicative of the processor's potential, then they would not have made such a big deal about the score during the presentation. They would have used some other benchmark.

Also, don't go around saying that it [IBM 970] barely out-performs an Itanium or Opteron since those aren't desktop CPUs! If you want to compare those to something, look at the POWER5 specs, or something.

Opteron is not a big-iron processor; it is the same league as the Xeon and this newly-announced IBM 970 processor for workstations and low-end servers (and likely desktop Macs). Opteron is simply a version of the "Hammer" Athlon with extra cache and a second DDR channel. Back in January, AMD said "Hammer" Athlons will be available for $200 by late 2003 (will obviously cost more when first released), while Opterons with 1Mb L2 cache for workstations and servers would offer significantly better price/performance than Xeon.

I have yet to see someone here articulate the benefits to the end-user of a 64-bit PowerPC processor, and a new version of OSX tailored for such a 64-bit processor. How does it help the average user running Photoshop or encoding MPEG4?

[Ken_F2]

Scott,

This is not the P4 thread. Try ars for that.

I didn't see you step in with a dozen or so other posters compared the 970 to the Pentium4 prior to my posts. The relative competitiveness of the 970 is of significant interest to many. There's been all sorts of talk in this post, and others, about a forthcoming IBM POWER4 derivitive that would destroy the P4 and Athlon.

I think many are interested as to whether the 970 will make Macintosh hardware competitive. I mean, isn't that the whole point? Isn't that why we're excited about this chip, because of the prospect that it will bring the Macintosh platform at least to parity, if not surpass the x86 platform? If you want to talk about the competitive landscape, or relative position of hardware platforms at around this time next year, then you can't avoid talking about what's on tap from other vendors. Certainly, IBM spent a good deal of time talking up the SPEC performance of the 970, and that's all we have to go on as far as it's performance and relative competitiveness is concerned.

[neilw]

These prolonged arguments about which vaporware processor will be faster a year from now are fruitless.

What I glean from the PPC970 discussion is that at some point in the next 12 months (plus or minus), the Mac will make a rather large quantum leap in performance, relative to what we've been living with with the G4. If it doesn't equal or outdo the best in the x86 camp, it will at least be back on the same playing field. That's good enough for me, for now. I am certainly more optimistic about the future of the Mac than I was when paltry G4 speed bumps were all we had to look forward to.

For me the big question is when, and how will Apple make it from now until then without falling further hopelessly behind.

[Superchicken]

you know, these troll posts are really big, and they're choking my poor 333Mhz G3. Please be respectful of those who don't have the cash for G4s right now... or who arn't willing to use crappy celerons like you trolls.

[moki]

Originally posted by Ken_F2:
I don't follow. IBM is expressly using these SPEC benchmarks in its MPF presentation to paint a picture of the 970's performance. If they didn't believe the SPEC score was indicative of the processor's potential, then they would not have made such a big deal about the score during the presentation. They would have used some other benchmark.

Unfortunately, no -- SPEC INT and FP are, largely due to Intel's enthusiasm, an industry standard. Processor manufacturers are about as likely to omit SPEC scores as car companies are likely to omit the car's BHP.

...and the people who know cars understand that horsepower is an interesting but mostly irrelevent measure of a car's performance. There are innumerable factors that determine a car's real world performance (weight, torque, tires, trany, the road you drive it on, etc., etc), just as there are innumerable factors that determine the kind of performance you'll get out of a processor.

If you want to run SPEC INT and FP on your machine, by all means, get a Pentium IV (or better yet, an Itanium 2) -- if you think your computer might be slightly more interesting doing something else, though, then you'll have to do what any car aficiando would do: take it for a drive.

If you think I'm being trite here, I'm not -- it really is the height of stupidity to believe that a set of benchmarks says anything other than how fast the processor can do those specific benchmarks. If you think what SPEC INT and FP measure in a CPU is what CPUs are asked to do on a regular basis, I've got a few bridges to sell ya...

Nevertheless, the PPC 970's estimated SPEC INT and FP scores are nothing to sneeze at, nor is the memory bus bandwidth, 16 way SMP capability, and innumerable other killer features of this chip. It's starting at around 1.8ghz, and moving right along to a .9 process and ever-higher clockspeeds.

Given the pipeline depth, I see no reason why IBM can't ramp this processor up to the same clockspeed as the P4 chip is now -- and given its more favorable IPC, that means it has legs...