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NewsPoster Apr 3, 2013 09:57 AM
Hybrid Memory Cube standard completed by consortium
The Hybrid Memory Cube Consortium has <a href="" rel='nofollow'>published</a> its first specification for <a href=" ogy/" rel='nofollow'>HMC</a>. Specification 1.0, after <a href="" rel='nofollow'>17 months</a> of work by the companies forming the consortium, details how manufacturers can create platforms and RAM using 2GB, 4GB, and 8GB chips, offering high-speed memory architectures that are also power-efficient. <br />
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HMCs use a number of memory wafers stacked on top of each other, using silicon Vertical Interconnect Access (VIAs) technology to pass electrical signal between layers. <br />
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The new specification tells of the how a HMC with eight links could hit a peak of 160Gbps of bi-directional bandwidth, <a href=" h_by_15X" rel='nofollow' target="_self" title="">writes</a> <em>Computer World</em>. By comparison, current-generation DDR3 is capable of 11Gbps of bandwidth for communication with the processor. A blueprint for the next generation, expected to be completed by early 2014, suggests that modules with individual data link speeds of up to 28Gbps, pushing the 160Gbps figure even higher. <br />
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The first products offering the new standard are not expected to surface until later this year.
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