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Metzen · Sep 16, 2001, 08:47 PM

IBM's 750CXe is now a dead chip. Yes, it maxes out @ 700mhz. Regardless of what "News sites" say, the 750CXe does not and will not go above 700mhz (according to IBM's Roadmap). This effectively concludes the G3 from active service. The only possible upgrade Apple could do to the iMac's is introduce them with a 133mhz bus (which is what the 750CXe was originally designed for) or go with a newer, faster chip.

Of other interesting tidbits of info for you all to chew on, IBM is almost about ready to introduce low-k dielectric into the manufacturing process as well as Cu-11 (copper chips @ 0.11 microns)
Pictures of a commercial Cu-11 chip.
Picutres of Cu-11 chip under a electron microscope, color enhanced.

Pictures of low-k dielectric surrounding copper wires under a electron microscope.

Picture of Cu-11 against 16 gauge shielded wire.

Beyond that, let's talk about the G5. Now, Motorola and IBM "seperated" during the development of the G4. Hogwash. IBM simply decided not to produce a G4 and Motorola decided it should. Both companies are still working together, very tightly together I should add.

Anyone else remember Motorola's new SiGe fab tech? Well... Guess who helped develop it?
IBM has fab plant's developing SiGe chips already. But we'll never see SiGe chips in Apple computers. Why is that?

Well... I'm sure a 0.35 micron process technology will stop the transistor count/mm2 as well as increase heat and voltage costs. So... It's NOT EVER going to happen any time soon.
So to recap...

We know that IBM and Motorola are working together again bringing joint technologies into the world together (albeit one company recieving the publicity [ok, so Motorola invented it first and that gives them the rights, whatever])
The PowerPC 750CXe tops out @ 700Mhz until the "next generation" chip is introduced before we see faster Mhz speeds out of IBM.
The "Next Generation" chip will need a few of the key technologies Motorola has (RapidIO, etc) and Motorola's "Next Generation" chip will be using a 0.13 micron SOI (only one company has fab's that can do SOI presently) and promises a bunch of other stuff that IBM already has.

(presently it looks like Motorola is waiting for IBM's SOI and 0.13 micron process to be introduced into it's BlueLogic first to cheapen production costs)

The G5 is going to rock. IBM's Power4 is slated to be released before the end of 2001 and the G5 looks set to go into production Q4 2001.

Little do people know but IBM is looking to invent two new markets with the Power4 and G5...

(Super/Ultra) Highend and Lowend servers to handle simple databases (lowend) or the super complex databases (highend) that we're starting to see today with room to grow.

That's it for today's lesson.

[ 09-16-2001: Message edited by: Metzen ]

Sep 16, 2001, 09:12 PM

Originally posted by Metzen:
IBM's 750CXe is now a dead chip.

Freakin' hell! So that's why all my Macs have stopped working this morning.

guerro · Sep 16, 2001, 09:22 PM

Dead chip ? Whaaa ?

Nimisys · Sep 17, 2001, 02:25 AM

Originally posted by Metzen:

The PowerPC 750CXe tops out @ 700Mhz until the "next generation" chip is introduced before we see faster Mhz speeds out of IBM.
The "Next Generation" chip will need a few of the key technologies Motorola has (RapidIO, etc) and Motorola's "Next Generation" chip will be using a 0.13 micron SOI (only one company has fab's that can do SOI presently) and promises a bunch of other stuff that IBM already has.

([ 09-16-2001: Message edited by: Metzen ]

excellent post however there is one thing i question... the SOI

AMD is currently outfitting its Dresden MegaFab (the one Moto leases) with .13micron and SOI. in fact there are rumors that its Hammer line (which is SOI and .13Micron)is sampling which means it has an SOI capabilities as well.

but like i said great post

itpga · Sep 17, 2001, 05:36 AM

Sounds really optimistic about the G5 beeing produced i Q4 this year. I started the "New G4...." thread and people talked about no changes before MWSF and no G5 until mid 2002 (MWNY or developer conference).
So it sounds great if true.

Cipher13 · Sep 17, 2001, 05:53 AM

Originally posted by itpga:
Sounds really optimistic about the G5 beeing produced i Q4 this year. I started the "New G4...." thread and people talked about no changes before MWSF and no G5 until mid 2002 (MWNY or developer conference).
So it sounds great if true.

Remember though; just cause the chip is out then doesn't mean the next PowerMac will utilise it within a month... it could be 6 months or so...

Metzen · Sep 17, 2001, 06:30 AM

Originally posted by Nimisys:


excellent post however there is one thing i question... the SOI

AMD is currently outfitting its Dresden MegaFab (the one Moto leases) with .13micron and SOI. in fact there are rumors that its Hammer line (which is SOI and .13Micron)is sampling which means it has an SOI capabilities as well.

but like i said great post

IBM beat out Motorola for the licensing rights to SOI for the AMD processor (article is outdated, IBM won). This translates into big $$$ for IBM. BUT(!) Motorol and AMD were already working on a SOI process as well as other joint tech's (low-k dielectric, copper interconnects, etc.) so they don't have to pay IBM for the licensing rights. A kind of funny thing is going on though... AMD has outfitted it's Dresden plant with IBM's fab tech. It's odd because they are going to use Motorola's SOI process, so AMD is going to pay for the fab technology, but not for the process tech (you have to pay seperate licences).

So, yes, your correct AMD does have a SOI plant, but it's using IBM's fab technology, and IBM's plants are the only one's making commericially available chips.

Meanwhile, AMD/Motorola are still working out some kinks in their processing technology, but, yes, some Hammerhead's have sampled. Unfortunately, apparently the errata is a show stopper. They believe (with good reason I'd imagine) that it's the process technology, not the chip itself, that is the source of their problems.

Anyways, what does this translate to for Motorola? Well... They're essentially getting the R&D of the SOI for free (minus the cost of a few engineers) AND studying how IBM outfits it's fabs (the Dresden plant) for it's own plants. Essentially, AMD paid IBM to license the fab tech and Motorola gets to look at the plans for free.

Anyways, I kind of bantered when I started this topic, but I predict the iMac's are going to sit at 500mhz - 600mhz - 700mhz with a few moderate changes (LCD??? It doesn't matter to me, but it'd be damn cool) the (2nd?) biggest being a move to 133Mhz busses. I encourage those with current model iMac's to OC your bus to 133Mhz. The processor is native to that speed and the gains are significant:

<BLOCKQUOTE>code:<HR><pre>
Tests 100Mhz 133Mhz
Mhz Speed 400Mhz 400Mhz
SPECint95_Peak 17.4 18.2
SPECint95_Base 16.2 17.0
SPECfp95_Peak 11.7 14.0
SPECfp95_Base 11.5 13.6
Dhrystone 2.1 MIPS 928 928
[/code]

The greatest gains are seen in the FPU where there is nealy a 20% gain in FPU performance over a 100Mhz bus.

And to end it off, (Does OSX really need the MacOS ROM?) could we see this board in a future Macintosh?

Specs:[LIST][*]2(!) 750CXe chips @ 700mhz connected through coreconnect (ASM through CoreConnect technology)[*]133mhz bus[*]1 SCSI-3 port[*]2 ATA 100[*]4 USB Ports[*]6 PCI slots
To answer the question anyways, NO, we will not see this board in a future mac, but I wonder if it'd work in MacOSX regardless... Hmmm...

So, to end it:
To those who wish for the demise of the G3, your going to get it, soon. There is one possible revision left (the move to 133mhz bus, Apple is petty, they will do this) that Apple can do to the G3 before it's forced to abandon it for the G4. With current G4 bus speeds at 133Mhz, I can see Apple moving the iMac's there first, then the revision after that adding G4 chips. That gives Apple a timeframe of about a year (MWNY) to introduce the G5's into the highend machines (assuming 2 revisions a year). So, either we'll see new G5 chips at MWSF or at MWNY either way, they're coming next year (<Q4 2002).

How high can the G4 go? I remember when MOSR said they were sampling the 7450 @ 1.2Ghz, this is hogwash. That's not how fab's work. Presently, Motorola is pumping out chips 2 to 3 months ahead of a product launch with super strict error checking on the chip(s) to work out bugs prior to launch (2 different versions of chips on the new Quicksilver's) then after that time, if all is well and the chips tested passed them, they announce it and start bulk manufacturing. Needless to say, there is no such thing as a prototype 8 chip 1.2Ghz G4 laptop roaming Apple's grounds. Manufactureer's keep ahead of current production by "1" generation usually, no more, no less (the exception being Gala's like the Microprocessor exhibit, etc).

[ 09-17-2001: Message edited by: Metzen ]

[ 09-17-2001: Message edited by: Metzen ]

Metzen · Sep 17, 2001, 07:29 AM

Originally posted by Metzen:

(presently it looks like Motorola is waiting for IBM's SOI and 0.13 micron process to be introduced into it's BlueLogic first to cheapen production costs)

The G5 is going to rock. IBM's Power4 is slated to be released before the end of 2001 and the G5 looks set to go into production Q4 2001.

I guess I should explain what BlueLogic is...

It's IBM's codename for there mainstream process technology. That is, every (excluding specialty chips) are made with these technologies. IBM is ahead of everyone else in outfitting "specialty labs" (read application specific integrated circuit (ASIC)) with technology two years or so ahead of everyone else (Cu-11 NOW, SOI in 1999, Copper in '96) and charges insanely high fees for your/their chip to be fabbed on these new process technologies. Afterwards, to win clients IBM annonces that these technologies will make their way into all of their fabs (minus the CMOSRF fab's which do SiGe, etc and can't do Cu-11, etc.) thus making its way into there mainstream chips, which the clients then recieve at no extra cost. This is what Motorola is waiting for IBM to do (if they haven't done so, I suspect that if IBM hasn't, they will within the next 2 months) so they can fab the SOI G5's.

BUT(!) it's not the SOI Motorola is waiting for, it's the .13 micron Cu (or will Motorola use Silicon? Hmmm...)
Anyways... Right now, IBM has 0.18 micron tech in it's BlueLogic lineup. As soon as the G5 whatever is announced, I bet we'll see 0.13micron replacing 0.18micron in that lineup...

Metzen · Sep 17, 2001, 08:34 AM

http://www.theregister.co.uk/content/39/21692.html

Not sure about certain parts of the article... This is definitely not Apple's though...

Speaking of which, we hear work is progressing on a new chipset, designed for the G5, which will support up to 16GB of DDR SDRAM. What type of DDR, we don't yet know. The chipset's south-bridge part - ie. the chip that primarily handles I/O - will support USB 2.0 and the Bluetooth wireless connectivity standard, in addition to the familiar 1394 - up to 800MBps? - and 802.11 (aka AirPort).

And this is hogwash:

So claim sources said to be close to Apple, at any rate. The new CPU will be offered at 800MHz, 1GHz, 1.2GHz, 1.4GHz and 1.6GHz, and while the first two are nominally aimed at the embedded space - the others are aimed straight at the desktop, we hear...

They are all the same chip (or are they???). If they are, then they are ALL aimed at the desktop. You need 2 different versions of chip (a lower power one and a high powered one) for embedded and desktop markets.

And this is hogwash:

That's said to be twice the 7450's transistor count, which makes us wonder what Motorola will do with the extra gates. The longer pipeline and additional instruction units will account for a lot of it, but we also wonder if the chip will feature a built-in memory manager, something Motorola has been talking about of late.

Either they aren't talking about chips Apple uses or there on crack. It's IMPOSSIBLE to make a modern CPU in a desktop computer without a memory manager. This makes me question the credibility of this whole article, or whether the writer is simply "hypothesising" that Motorola chips lack a Memory Manager.

I also can't see how a "simple recompile" is all that's needed to make a 64bit app. Run at 32bit full-speed? No problem, it's just a matter of switches for ensuring 64bit registers only address 32bits and enabling the other 32bits to be used as well. The trick, no doubt, is to ensure that these 32bit registers work / cycle. Usually a proc will wait for a register to fill (read: waste of 32bits of space). How does it do that? Well... a program sends a 32bit instruction to the 64bit address/register. Since the proc wants to do the instruction in one cycle it wastes 32bits of addressing space. I wonder how they fixed that. Apparently, Itanium wastes the 32bit of addressing space, I'd have to check to be sure though...
Undoubtedbly this assurance of full 32bit support @ full speed is what cropped up the higher transistor count. But to address 64bit's of space on a recompile? Eeek! That'd have to be some peice of hardware/compiler combo. Addressing 64bits of data is waaaaaaaaaaay more then 32bits. I bet the integer/fpu scores on it just fly.

It will truly be interesting if Apple introduces the lower end G5 spectrum (800mhz, 1Ghz, 1.2Ghz) and leaves the 1.6Ghz for the upgrade companies to work on (I'd love to see a 1.0Ghz G5 in my iMac DVSE...)

I'm interested in how big this monster is though...

Hmmm... Well... a PowerPC 750CXe 5 layer (or is it 8?) Cu-18 chip is 42.7mm2 @ 20million transistors.

Since mass is pretty well constant, we can assume a Cu-13 chip is 72% smaller. This would make the 42.7mm2 die 30.8mm2 @ 20million transistors. Now, according to the register, the G5 is 58 million transistors.

This is 2.9x larger which puts the beast at or around 89.3mm2. Eeek!!!

The Itanium Core (no L2 cache) is only 25million transistors. The 4meg L2 cache adds 300million transistors. This proc is going to be 325 million transistors! Couple that with a die size of 469mm2...

I wonder how the G5 will do against the Itanium...

[ 09-17-2001: Message edited by: Metzen ]

Nimisys · Sep 17, 2001, 11:39 AM

IBM beat out Motorola for the licensing rights to SOI for the AMD processor (article is outdated, IBM won). This translates into big $$$ for IBM. BUT(!) Motorol and AMD were already working on a SOI process as well as other joint tech's (low-k dielectric, copper interconnects, etc.) so they don't have to pay IBM for the licensing rights. A kind of funny thing is going on though... AMD has outfitted it's Dresden plant with IBM's fab tech. It's odd because they are going to use Motorola's SOI process, so AMD is going to pay for the fab technology, but not for the process tech (you have to pay seperate licences).
So, yes, your correct AMD does have a SOI plant, but it's using IBM's fab technology, and IBM's plants are the only one's making commericially available chips.

Meanwhile, AMD/Motorola are still working out some kinks in their processing technology, but, yes, some [Claw/Sledge] Hammer's have sampled. Unfortunately, apparently the errata is a show stopper. They believe (with good reason I'd imagine) that it's the process technology, not the chip itself, that is the source of their problems.

thnx for clearing that up for me... <ignorant mode> looks like moto is screwing someone over again </ignorant mode>

you mentioned errata making the Hammer a showstopper, seeing as you got links to everything else out there, any links for this, or what the errata is

intrested because the Hammer line will end up being the direct compitior to the G5

gumby5647 · Sep 17, 2001, 12:26 PM

i agree, the G3 is dead. It's 90's technology. bring on the G4 iMac please....

THT · Sep 17, 2001, 02:11 PM

Originally posted by Metzen:
Either they aren't talking about chips Apple uses or there on crack. It's IMPOSSIBLE to make a modern CPU in a desktop computer without a memory manager.

They were talking about the memory controller being on the microprocessor, not that there wouldn't be one. And the speculation isn't off the beaten track because the rumours for the G5 are that it will have a dual channel RapidIO bus and or a memory controller on the microprocessor. (The Sony Emotion Engine CPU in PS2 consoles have a dual channel Rambus memory controller on-die, so it isn't something that hasn't been done before.)

It will truly be interesting if Apple introduces the lower end G5 spectrum (800mhz, 1Ghz, 1.2Ghz) and leaves the 1.6Ghz for the upgrade companies to work on (I'd love to see a 1.0Ghz G5 in my iMac DVSE...)

I seriously doubt it since the Apollo G4 (7460), a 7450 fabricated with Moto's 0.13 micron SOI HiP 7 process, should ship at 800 MHz to 1.2 GHz. Power dissipation is expected to be 20 Watts for a 1 GHz chip and 10 Watts for a 700 MHz chip. I would expect these chips to be in new Power Macs at MWSF02. The 7440, 1.5V 7410, and maybe the low MHz 7460s (>800 MHz) for iMacs, iBooks and Powerbooks.

There will be no processor upgrades for any prior Mac because the G5 will use a new and different bus architecture (RapidIO, LDT and whatnot). The Apollo G4's could probably be used for upgrade cards since it uses the same MPX bus that's being used for Sawtooth socket Macs.

Hmmm... Well... a PowerPC 750CXe 5 layer (or is it 8?) Cu-18 chip is 42.7mm2 @ 20million transistors.

Since mass is pretty well constant, we can assume a Cu-13 chip is 72% smaller. This would make the 42.7mm2 die 30.8mm2 @ 20million transistors. Now, according to the register, the G5 is 58 million transistors.

This is 2.9x larger which puts the beast at or around 89.3mm2. Eeek!!!

IBM's 0.18 micron process has 6 layers of metallization. The 89.3 sq mm is nothing to worry about since Apple has shipped G4's with die areas of 83 sq mm (0.22 micron 7400, the first G4) and the 105 sq mm 7450 in the current G4 Macs.

58 million transistors sounds like they are using 512 KB of L2 cache. Motorola's floor planning on its chips aren't as agressive as IBM's, so I would expect the chip to be in the 100+ sq mm range.

What's to worry about are the power dissipation numbers. Things in the 20+ Watt range will necessitate a noisy fan system.

re: G3 is a dead chip

The iBook still has 200 MHz of growth left, so it may use it for a awhile. And Apple may introduce some newer ultraportable or product category that'll require the cheaper and lower power G3 as well. So, I don't it's dead yet.

sek929 · Sep 17, 2001, 03:28 PM

Originally posted by gumby5647:
i agree, the G3 is dead. It's 90's technology. bring on the G4 iMac please....

Pfft! I'm still using (quite happily mind you) a 601e at 120mhz.....

Nothing is dead in the tech world until you stop using it...and Im' sure the G3 will be used for many many years to come.

Frankly all this talk about processor power is hogwash (a word I heard frequently) since once these latest greatest things become 3 months old there "dead" already. The tech world is to fickle to get excited about new speeds and such. I say but the fastest thing now and squeeze all the life out of it you can intstead of waiting for the next big thing.

As for you G5 hopefuls....lets just recap how long Apple was at 500mhz with the G4, I'm sure we won't see one in an Apple line till mid next year at the earliest.

Metzen · Sep 17, 2001, 04:09 PM

[quote]Originally posted by THT:
They were talking about the memory controller being on the microprocessor, not that there wouldn't be one. And the speculation isn't off the beaten track because the rumours for the G5 are that it will have a dual channel RapidIO bus and or a memory controller on the microprocessor. (The Sony Emotion Engine CPU in PS2 consoles have a dual channel Rambus memory controller on-die, so it isn't something that hasn't been done before.)


That's not what RapidIO is for! Don't confuse RapidIO with Rambus! RapidIO is a new way to connect the chips on a motherboard so that data travels faster from point A to point B (up to 64 Gigabits/sec!). In other words, it can increase the total bandwidth of the PCI bus so that "designers can now configure PCI-oriented systems containing hundreds of PCI or PCI-X slots." AND RapidIO works with Rambus, it doesn't compete with it. RapidIO specifically competes against InfiniBand.
RapidIO also works with current memory controller solutions to increase overall bandwidth as well. Essentially, RapidIO increases bandwidth through a new means of interconnecting devices/chips on the motherboard. It was initially designed for high input/output networking but has evolved since then.

[QUOTE]Originally posted by THT:
I seriously doubt it since the Apollo G4 (7460), a 7450 fabricated with Moto's 0.13 micron SOI HiP 7 process, should ship at 800 MHz to 1.2 GHz. Power dissipation is expected to be 20 Watts for a 1 GHz chip and 10 Watts for a 700 MHz chip. I would expect these chips to be in new Power Macs at MWSF02. The 7440, 1.5V 7410, and maybe the low MHz 7460s (>800 MHz) for iMacs, iBooks and Powerbooks.


Where are you getting these numbers for the 7460? Motorola has nothing on Apollo at there website or research sites. My suspicision is that Apollo will be a functionally equivalent 7450, with lower wattage usage and better "speedstep" technology builtin. I always thought this was Apollo with a name change. It contains MANY of the features Apollo is susposed to have... Perhaps they changed the name?
1.5v 7410 doesn't exsist. It's 1.8v

Originally posted by THT:
There will be no processor upgrades for any prior Mac because the G5 will use a new and different bus architecture (RapidIO, LDT and whatnot). The Apollo G4's could probably be used for upgrade cards since it uses the same MPX bus that's being used for Sawtooth socket Macs.

No it doesn't. The Apollo is susposed to follow the same specs as the 7450 which won't work in any computer <733Mhz.

That and RapidIO is made to exsist concurrently with MPX bus and actually enhance it.

IBM's 0.18 micron process has 6 layers of metallization. The 89.3 sq mm is nothing to worry about since Apple has shipped G4's with die areas of 83 sq mm (0.22 micron 7400, the first G4) and the 105 sq mm 7450 in the current G4 Macs.

58 million transistors sounds like they are using 512 KB of L2 cache. Motorola's floor planning on its chips aren't as agressive as IBM's, so I would expect the chip to be in the 100+ sq mm range.

What's to worry about are the power dissipation numbers. Things in the 20+ Watt range will necessitate a noisy fan system.


I'm hoping for a larger L1 Cache vs. a larger L2 cache on the G5. a 128kb+ cache would kick ass. One of the Athlons major speed enhancements was to move to a 128kb L1 Cache.

The iBook still has 200 MHz of growth left, so it may use it for a awhile. And Apple may introduce some newer ultraportable or product category that'll require the cheaper and lower power G3 as well. So, I don't it's dead yet.

What I meant is that a G4 iMac is really close. If not MWNY, then MWSF for sure.

THT · Sep 17, 2001, 05:31 PM

Originally posted by Metzen:
That's not what RapidIO is for! Don't confuse RapidIO with Rambus!

I'm not. That's why I said "and or". It's rumours after all. But I've heard about onboard memory controllers for the G5 from AI discussions prior. (AI, AppleInsider, had a few people who would be in a position to know about future hardware.) And it would not be very surprising to see a DDR SDRAM or Rambus memory controller on the microprocessor die for the G5.

Where are you getting these numbers for the 7460? Motorola has nothing on Apollo at there website or research sites. My suspicision is that Apollo will be a functionally equivalent 7450, with lower wattage usage and better "speedstep" technology builtin. I always thought this was Apollo with a name change. It contains MANY of the features Apollo is susposed to have... Perhaps they changed the name?
1.5v 7410 doesn't exsist. It's 1.8v

The Apollo G4 was revealed at last year's Microprocessor Forum. Several news report say:

Moto's Apollo program to boost G4

SAN JOSE, CALIF. -- Motorola has announced its own Apollo program, the code name for a new generation of PowerPC G4 chips that will finally break the 1GHz barrier. ... Based on Motorola's previous V'ger design -- disclosed at last year's Microprocessor Forum -- the Apollo chips will use Motorola's now-perfected 0.18-micron copper manufacturing process as well as silicon-on-insulator (SOI) technology to boost performance further. The chip will offer full software compatibility with existing G3 and G4 designs and will provide built-in multiprocessing support. ... The chip's typical power consumption will be less than 23 watts at 1GHz, Motorola said. The company will make it available to both the desktop and embedded markets, offering the ability to trade frequency for energy conservation. The chip should use less than 10 watts at 666MHz.

I originally believed that Motorola would fabricate chips with SOI at 0.18 micron, but I have to believe they have moved SOI to 0.13 micron now, since it doesn't seem like the MHz boost that SOI was marketed to give is panning out. The 1.5V 7440 at 700 MHz dissipates 17 Watts. I would presume Apollo at 0.13u would operate at 1.5V as well, but with the addition of 0.13 micron and SOI (20 to 30% reduction in power), it'll get the power down to 10 Watts at 700 MHz.

As for the 1.5V 7410, it was announced last May:

Motorola Introduces PowerPC Host Processors Designed for Low Power, High Performance Embedded Applications

SMART NETWORKS DEVELOPER FORUM, NEW ORLEANS - May 21, 2001 - Further enhancing the ever-growing Smart Networks product portfolio, Motorola, Inc. (NYSE: MOT) today announced the MPC7440. ... In addition to the MPC7440, Motorola also announced today a low power version of the MPC7410 processor available at 450MHz. ... The popular MPC7410 processor is being offered at 450MHz with a typical power usage of 3.5W running at 1.5V. ... In addition, both the MPC7440 and MPC7410 are manufactured using the HiPerMOS 6 (HiP6) 0.18-micron copper fabrication process technology. ... The MPC7440 processor is expected to begin sampling in 3Q01 with production slated for 4Q01. The advanced low power version of the MPC7410 is expected to begin production in 3Q01.

No it doesn't. The Apollo is susposed to follow the same specs as the 7450 which won't work in any computer <733Mhz.

That and RapidIO is made to exsist concurrently with MPX bus and actually enhance it.

Apollo uses a MPX bus, so it will be compatible with all Sawtooth socket Macs. The MPX bus is a parallel bus. It is quite incompatible with the serial RapidIO bus. If the G5 supports the MPX bus, it can be used in upgrade cards, but if it doesn't, and all signs point to it using a new bus topology (RapidIO), it most certainly will not be used for upgrade cards unless someone makes a bridge chip for it a la Rambus ASIC Cells.

Sep 17, 2001, 05:33 PM

Metzen,

I do not think THT is confusing RapidIO with Rambus. He was using the PS2 as an example. If Motorola integrates a memory controller into the G5, you would still need RapidIO or something for the front side bus. With an integrated memory controller you reduce memory latency. Current CPUS, G4s, P4s, or Athlons, the FSB is conected to the NorthBridge/Uni-North where the memory controller among other things is located. Your ram is tied to the memory controller.

cheers,

alex

Metzen · Sep 17, 2001, 09:53 PM

Originally posted by Nimisys:
you mentioned errata making the Hammer a showstopper, seeing as you got links to everything else out there, any links for this, or what the errata is

intrested because the Hammer line will end up being the direct compitior to the G5

Not chip errata, the fab process of attaining SOI @ Cu-13.

In the article they say the following:

"Already, the intro date for the K8 'Hammer' processor line has been pushed back substantially because of delays in the .13 and .13 SOI processes it requires. Intel, however, will be flaunting its .13 Northwood Pentium 4 in October of this year."

Now, this article was written in June. So, I'm not sure how much has changed already, if any. But I seem to recall PC rumor sites (much more reliable then Mac rumor sites :rolleyes

saying the Hammer series of AMD proc's being relased Q4 2001. This was, again, a while ago though, so take it as it is.

Metzen · Sep 17, 2001, 09:58 PM

Originally posted by <Dual Athlon>:
Metzen,

I do not think THT is confusing RapidIO with Rambus. He was using the PS2 as an example. If Motorola integrates a memory controller into the G5, you would still need RapidIO or something for the front side bus. With an integrated memory controller you reduce memory latency. Current CPUS, G4s, P4s, or Athlons, the FSB is conected to the NorthBridge/Uni-North where the memory controller among other things is located. Your ram is tied to the memory controller.

cheers,

alex

Ok, a memory controller is different then a memory manager. But, it doesn't matter if the FSB can run at 400mhz if you don't have RAM fast enough to achieve this speed. Sounds like the G5 is poised to use Rambus...

ThunderP · Sep 17, 2001, 10:39 PM

The chipset's south-bridge part - ie. the chip that primarily handles I/O - will support USB 2.0 and the Bluetooth wireless connectivity standard, in addition to the familiar 1394 - up to 800MBps? - and 802.11 (aka AirPort)

i thought that airport and bluetooth used signals that interfered with each other, dosent that make this setup impossible and pretty much debunk the whole article?

Metzen · Sep 17, 2001, 11:10 PM

Originally posted by ThunderP:


i thought that airport and bluetooth used signals that interfered with each other, dosent that make this setup impossible and pretty much debunk the whole article?

That's why you specialize. Put support for both on one motherboard to reduce manufacturing costs of two different motherboards and then just add whatever controller the customer is asking for, be it either bluetooth or 802.11b. I'm not 100% sure about the incompatibilities though, I'll check it out later.

Whisper · Sep 17, 2001, 11:21 PM

Originally posted by ThunderP:


i thought that airport and bluetooth used signals that interfered with each other, dosent that make this setup impossible and pretty much debunk the whole article?

There's no rule that says you have to use both of them at the same time. Why couldn't there be a switchboxish system so only one of them is active at any given time?

Sep 17, 2001, 11:28 PM

Metzen- Whoa that board is sweet, do you know who makes it? Are those things available for me to buy? I could use one in my beige G3, would it work?

THT · Sep 17, 2001, 11:56 PM

The one reliable piece of information coming out of the Register article is probably that it taped out this month, which means a G5 chip may ship this Spring or Summer if we're lucky (sampling by December, pilot production by March and mass production by June). Everything else looks to be speculation to me.

RapidIO is a good bet since Moto has it on their roadmap for the G5. I've heard rumors for dual-core PPC chips for both Moto and IBM, so that could be a possibility. On-die memory controllers have been bandied about by both Moto and IBM for their next gen PPC chips. Pipeline depth of 10 stages doesn't sound too unreasonable. 64 bit with 32 bit backward compatibility is part of the Book E spec, so that won't be a big surprise.

400 MHz FSB, northbridge and southbridge specs look to be pure speculation to me. Especially considering that Apple currently bridges Firewire and Ethernet off of the northbridge, not the southbridge.

Sep 18, 2001, 05:01 AM

Originally posted by Metzen:

Ok, a memory controller is different then a memory manager. But, it doesn't matter if the FSB can run at 400mhz if you don't have RAM fast enough to achieve this speed. Sounds like the G5 is poised to use Rambus...

If you read the EETimes article, Motorola is talking about a DDR memory controller, not Rambus.

Why would the FSB speed of a chip with an integrated memory controller matter? The whole point of integrating the MC is to keep memory access off the FSB. Lets for a moment assume the G5 has a 400MHz FSB. I would bet it is a 200MHz 8 bit RapidIO port. The reason it is called 400MHz is the same reason Intel calls their quad-pumped 100MHz FSB a 400MHz bus, Maketing. Since RapidIO is double-pumped, a 200MHz port could be called 400MHz.

Now if the G5 has a 400MHz 8 bit RapidIO port and an integrated memory controller, that would rock. A 400MHz 8 bit RapidIO port, like a rambus channel, has 1.6GB/s of bandwith. 1.6GB/s for AGB, PCI, USB 2.0, Firewire2, Gig-E, and ATA-100. If the MC was a dual channel 166MHz DDR, you would have 5.2GB/s of memory bandwith. Note since the G5 is a 64bit chip you would need dual channel for memory.

cheers,

alex

Metzen · Sep 18, 2001, 05:57 AM

Originally posted by <TigerWoods99>:
Metzen- Whoa that board is sweet, do you know who makes it? Are those things available for me to buy? I could use one in my beige G3, would it work?

SBS Technologies hired IBM to do all the work on it. Sounds like there hoping to make a Linux box out of it to sell to the masses?

Link

Metzen · Sep 18, 2001, 06:27 AM

Originally posted by <Dual Athlon>:

If you read the EETimes article, Motorola is talking about a DDR memory controller, not Rambus.

Why would the FSB speed of a chip with an integrated memory controller matter? The whole point of integrating the MC is to keep memory access off the FSB. Lets for a moment assume the G5 has a 400MHz FSB. I would bet it is a 200MHz 8 bit RapidIO port. The reason it is called 400MHz is the same reason Intel calls their quad-pumped 100MHz FSB a 400MHz bus, Maketing. Since RapidIO is double-pumped, a 200MHz port could be called 400MHz.

Now if the G5 has a 400MHz 8 bit RapidIO port and an integrated memory controller, that would rock. A 400MHz 8 bit RapidIO port, like a rambus channel, has 1.6GB/s of bandwith. 1.6GB/s for AGB, PCI, USB 2.0, Firewire2, Gig-E, and ATA-100. If the MC was a dual channel 166MHz DDR, you would have 5.2GB/s of memory bandwith. Note since the G5 is a 64bit chip you would need dual channel for memory.

cheers,

alex

Yes, yes, yes, where did you find that RapidIO is "double-pumped"? I haven't seen that anywhere. And why does the G5 need a dual channel for memory? I was under the impression that if the memory can address 64bit's then everything's good. Current SDRAM/DDRAM can address up to 64bit's of addressing space and are used in IBM's 64bit Server Solutions.

So... Why do we need dual channel DIMM's? DDRAM/SDRAM works just fine in single channels, and 64bit chips can address DDRAM and SDRAM just fine because DDRAM and SDRAM both have 64bit address spaces...

Metzen · Sep 18, 2001, 06:45 AM

Originally posted by <Dual Athlon>:
Now if the G5 has a 400MHz 8 bit RapidIO port...

Ummm... All RapidIO specs say that RapidIO is 32bit. The only thing that's 8bit/16bit is the LP-LVDS (Low Voltage Differential Signalling) interface.

Sep 18, 2001, 02:21 PM

Originally posted by Metzen:


Yes, yes, yes, where did you find that RapidIO is "double-pumped"? I haven't seen that anywhere. And why does the G5 need a dual channel for memory? I was under the impression that if the memory can address 64bit's then everything's good. Current SDRAM/DDRAM can address up to 64bit's of addressing space and are used in IBM's 64bit Server Solutions.

So... Why do we need dual channel DIMM's? DDRAM/SDRAM works just fine in single channels, and 64bit chips can address DDRAM and SDRAM just fine because DDRAM and SDRAM both have 64bit address spaces...

The sampled is on both edges of the clock signal, hence 'double-pumped.'

I have an idea, try reading what you link. The IBM link is even better:

Memory |is supplied by 128, 256, and 512 MB DIMMs which must be mounted in banks of |eight DIMMs. Different capacity DIMMs (in banks of eight) can be mixed |on the memory cards.

So the POWER3 needs 8 banks of ram, how is it so hard to grasp that a G5 would need 2 DDR channels? I have a question for you, What is the smallest size of memory a CPU can get from main memory? Here's a hint, a cache line and a cache line != register size.

cheers,

alex

Sep 18, 2001, 02:35 PM

Originally posted by Metzen:


Ummm... All RapidIO specs say that RapidIO is 32bit. The only thing that's 8bit/16bit is the LP-LVDS (Low Voltage Differential Signalling) interface.

The RapidIO word size is 32 bits and your point is? How wide is the bus? 8 or 16 bits. A 8 bit LVDS interface would split a word into 4 parts and send it in 8 bit parts.

cheers,

alex

Metzen · Sep 18, 2001, 03:46 PM

Originally posted by <Dual Athlon>:


The RapidIO word size is 32 bits and your point is? How wide is the bus? 8 or 16 bits. A 8 bit LVDS interface would split a word into 4 parts and send it in 8 bit parts.

cheers,

alex

And AltiVec recieves data from a 32bit bus, but we don't call it 32bit. You judge bits by how data is processed internally from the device. Don't confuse the 2.

Originally posted by <Dual Athlon>:
The sampled is on both edges of the clock signal, hence 'double-pumped.'

I have an idea, try reading what you link. The IBM link is even better:

Where does it say that? Here's what the IBM link reads:

375 MHz POWER3 SMP High Nodes have one to four memory cards, require |a minimum of one GB of memory, and support a maximum of 64 GB. Memory |is supplied by 128, 256, and 512 MB DIMMs which must be mounted in banks of |eight DIMMs. Different capacity DIMMs (in banks of eight) can be mixed |on the memory cards.

|For the best memory-access bandwidth, memory DIMMs should be |distributed evenly across four memory cards. As an example, you can |realize better bandwidth by using four banks of 128 MB DIMMs (4 GB total) |distributed evenly over four memory cards rather than by using one bank of 512 |MB DIMMs (4 GB total) on one memory card. The following list |illustrates this: |

* |1 to 16 GB memory mounted on one card yields 16.8 - 24.3% of |peak bandwidth
* |2 to 32 GB mounted on two cards yields 33.5 - 48.5% of peak
* |4 to 64 GB mounted on four cards yields 67 - 97% of peak |

|The configurator rules used for memory placement in these nodes are |designed to yield the best memory performance. Any plans to increase |the amount of memory in the future should always be taken into consideration |when deciding what size DIMMs to use and the quantity of memory cards to |order.

It doesn't say anything about "double pumping" the RAM.

Please highlight the line where it specifies this.

gumby5647 · Sep 18, 2001, 04:09 PM

Originally posted by sek929:
[QB]

Pfft! I'm still using (quite happily mind you) a 601e at 120mhz.....

QB]

Ha! i got you beat! im using a 76Mhz (38Mhz, however you want to look at it) LC040 in a PowerBook Duo 280.

clash · Sep 18, 2001, 05:20 PM

Originally posted by gumby5647:


Ha! i got you beat! im using a 76Mhz (38Mhz, however you want to look at it) LC040 in a PowerBook Duo 280.

My wife still uses our Performa 560 (68030 @ 33mhz) for email & games!