[eddiecatflap]

..apart from the cpu?

..what ELSE is holding performance back?

..is their one component that sticks out like a sore thumb that you think just doesn't need to be there and could be changed for a superior item at very little cost ?

[Thain Esh Kelch]

Support for faster bus speeds, and therefore a significantly faster bus!

[Sarc]

Cables ... it's got to be the cables.

[D'Espice]

They would have to replace the Logicboard (Mainboard) in order to increase performance. The slow chipset with its 133/166 MHz Frontside Bus is holding performance back. The Frontside Bus needs to be as fast as the memory bus, meaning 133DDR/166DDR so memory access would be much faster.
However by doing so, Apple would also have to replace the current microprocessor because apparantly, the G4 is not compatible to DDR-Buses in Chipsets. Either Motorola has to change that or Apple has to replace the CPU.

[Simon]

Ditch DDR all together. Fast DDR at 266/533 is a no-go since the current G4 does not support anything else than a MaxBus at 166MHz. The CPU, not the bus is the bottle-neck. That's why there is almost no gain from the QS to the MDD at the same clock.

So, ditch DDR. Ditch the DDR hack in the MDDs.

New hack: dual and quad CPUs with L2 on die and 2MB L3 at full speed for each CPU. Each CPU has it's own dedicated MaxBus running at 166MHz and it's own SDRAM running at full MaxBus speed. The 2 or 4 MaxBusses meet at the system controller (which connects each CPU/RAM channel with the others and rest of the on-board components) which is connected to a FSB running at 266 or 533MHz so that it can feed all MaxBusses at their max speed at the same time. That should give the Mac quite a peformance kick and I suppose that would mean any P4 out there could be kicked by a quad 1Ghz PowerMac.

Will it happen? No. Why? I can't see Apple dedicating so much time, people and money towards building a system controller to overcome a chip's limitations that will probably not be here for more than a year. Additionally, these Macs would probably be pretty expensive. And they would require a RAM upgrade for each processor, i.e. you get 2*256 default on a dual system. If you want to upgrade to 512 you have to buy another two 256 DIMMs bercause each CPU has its own mem channel. That also makes the box more expensive.

But I believe if money were not an issue and the 970 were decades away this would be quite a good hack.

I figured since my description was a bit bumpy I could give you a small pic, but it's rather sloppy Nevertheless you get the idea...

[DrBoar]

Can anyone point out a test were the Powerlogic dual 1GHz in AGP mac with a 100 MHz bus is compared with the current dual 1GHz that has a 167 Mhz bus?
If the difference is marginal (<20%) it suggest that the bus si not the limiting factor and thus the old AGP versions should scale well with singel CPU upgrades in the 2-3 GHz range at least and duals in 1-1.4 GHz..

Unless proven otherwise the 3 major bottlenecks are CPU , CPU and CPU!

[Simon]

Originally posted by DrBoar:
Unless proven otherwise the 3 major bottlenecks are CPU , CPU and CPU!

Yes and no. The CPU is the bottleneck if you are talking about the CPU's bus. Moto's MaxBus architecture used in G4s is bandwidth-limited, yes. And the G4 relies on this MaxBus so we are stuck as long as we have this G4. There are however rumors about the next revision of the G4, the 7457, which should be able to "talk" with the board over a normal DDR bus.

If you think the CPU is a bottleneck because it can't supply more data than a DDR bus can push you are wrong. A single Altivec unit can peak at about 3.2GB/s which is much more than a MaxBus can feed.

You have to be clear as to which "CPU bottleneck" you are talking about.

Beacuse the G4 can process data at much higher rates than it can push through its MaxBus I came up with the hack showed above.

[Thain Esh Kelch]

Originally posted by Simon:
Will it happen? No. Why? I can't see Apple dedicating so much time, people and money towards building a system controller to overcome a chip's limitations that will probably not be here for more than a year.

Who says it hasnt already been done, and that the next 2/4x1,4 Ghz Powermacs will future this?

[freakboy2]

That's why they have the L1 and L2 caches. Once the data gets there, it gets accessed really fast. Even if you perfectly optimized ALL the ram to go as fast as the CPUs might need, you wouldn't see as much of a benefit as you might think.

I'd vote for faster CPUs.

FB2

Originally posted by Simon:


Yes and no. The CPU is the bottleneck if you are talking about the CPU's bus. Moto's MaxBus architecture used in G4s is bandwidth-limited, yes. And the G4 relies on this MaxBus so we are stuck as long as we have this G4. There are however rumors about the next revision of the G4, the 7457, which should be able to "talk" with the board over a normal DDR bus.

If you think the CPU is a bottleneck because it can't supply more data than a DDR bus can push you are wrong. A single Altivec unit can peak at about 3.2GB/s which is much more than a MaxBus can feed.

You have to be clear as to which "CPU bottleneck" you are talking about.

Beacuse the G4 can process data at much higher rates than it can push through its MaxBus I came up with the hack showed above.

[Simon]

Originally posted by Thain Esh Kelch:

Who says it hasnt already been done, and that the next 2/4x1,4 Ghz Powermacs will future this?

Well believe me, I would love to see it happen. And I would go mug people on the street to get the moeny for such a Mac. Well, OK, I wouldn't mug them, but I'd sell one of my kidneys...

I really doubt that Apple has done something like this in the mean time. If they had, why the intermezzo of DDR? You could say marketing, but I suppose you can't just rip out SD and put in DDR in a couple of hours just because some 22 year old marketing goof with a tie came over and said people will only buy Macs if they have DDR. If Apple had this coming they would have just given us the higher clocked G4s and the new MDD case without the DDR, don't you think?

How the hell is Apple supposed to tell people:
- last year: well, we are the fastest on the planet with SD
- this year: well, we are now using DDR which makes us the fastest
- next year: well, we ditched DDR because our new quad busses are much faster

Why would Apple so this kind of back and forth?

I don't know of course, but I believe it's more likely that Apple could intro a 7457 with native DDR support. That would be in line with the MDDs. They were ready with DDR before Moto was ready with the 7457. Just a guess...

[Simon]

Originally posted by freakboy2:
Even if you perfectly optimized ALL the ram to go as fast as the CPUs might need, you wouldn't see as much of a benefit as you might think.

I'd vote for faster CPUs.

LOL. freakboyTWO, everybody wants faster CPUs. Tell me something new. But what if I tell you that all Moto has is 1.4GHz 7455 and the 7457 isn't nearly ready. Now what? Yeah right, we're screwed royally up the butt.

I can tell you what my hack would do in theory, but I admit this is just theory - not everyday stuff.

Presently when Altivec kicks in (or our INT units go to full blast) and makes our Macs perform really well we are only seeing part of the show. A rather small part actually. Altivec can produce 3.2GB/s of data. I have a MDD, so I have two Altivec units peaking at 6.4GB/s. They both shove the data out the front door to the U2 (that is Apple's name for the system controller doing the DDR hack) at no more than 166MHz (together! i.e. each has only 83MHz). My RAM is sitting on it's DDR which would be ready to take 333MHz. So 2x 83MHz is by no way pushing it and the best part is the 166MHz MaxBus can't even handle the 3.2GB/s of a single chip.
Now imagine we go quad processors. We have 4x3.2GB/s going over a mere 166MHz going to the U2 and now we have a huge bottleneck because even if the U2's backyard is 333MHz we have 4 G4's sharing one single MaxBus at 166MHz. So basically this means that the G4's get slowed down to pumping out data at 166MHz / 4 = 42MHz. Cool, we have just invented a Macintosh IIfx with a G4. And bravo, we have just lost 87% of our CPU-to-mem bandwidth (333MHz / 42MHz = 7.9!!!). Altivec which supplies more than the 166MHz MaxBus can handle on one chip anyway is now sitting there idling away, getting bored and taking dust.

That sucks. This is why we need another approach if we want quad systems. And we want quad systems since in OS X we expect quad systems to push performance noticeably. You will see that with my above approach we don't encounter such a bottleneck. I am however not sure how easy it is to make the required system controller. Maybe that's a real electrical engineering nightmare. I don't know. I also don't think Apple would do something like this as I pointed out in the post before this one. I just like the idea and I believe this would have been a much better architecture than the DDR hack introduced with the XServe. Nevertheless I love it - it's part of my great MDD PowerMac.

[freakboy2]

Yeah, so I still want a faster proc. :-)

I see your point. Optimizing the system as you suggest would improve the performance assuming that 100% of the time it's using altivec and 100% of the time it's trying to move that data back to the RAM. Maybe someone who designs cpu's can chime in here, but I don't think that's really what happens.

FB2

[CheesePuff]

Full altivec support in OS X.

[freakboy2]

wheels and long power cord

[Amorph]

I think Simon's on to something, except that he's either got the G4 sporting two MaxBusses or two L3 cache busses.

It would probably be simpler to have two G4s, each with its own MaxBus, fed by the memory controller from a common pool of memory. It would require an agile memory controller, but since the RAM currently has twice the bandwidth of MaxBus, it makes sense from a systems engineering POV.

The biggest gotcha (says the software guy with no background in HW engineering ) would be maintaining cache coherency between the two processors, since they apparently depend on a shared bus architecture to handle that?

The biggest practical obstacle would be throwing a lot of time and money into a board that wouldn't last very long, unless the 970 hits a real snag (heaven forfend). Or unless Apple follows the 970 intro by shipping DP PowerBook G4s and iMacs. Ha.